2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)最新文献

{"title":"Thermosonic ball bonding behavior of Ag-Au-Pd alloy wire","authors":"Santosh Kumar, Hoontae Kwon, Young I. L. Heo, S. H. Kim, J. Hwang, J. Moon","doi":"10.1109/EPTC.2013.6745675","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745675","url":null,"abstract":"Thermosonic wire bonding is a well-known process which combines heat, ultrasonic energy and force to bond small wires to complete an electrical path from a metalized surface on a microchip to another metalized surface on the substrate of the circuit and the bonding occurs through the process of atomic diffusion. The bonding wire materials presently used in the industries are primarily gold (Au) and recently the use of low cost copper (Cu) and palladium coated wire (PdCu) have increased significantly. However, due to the increasing price of Au and reliability concerns with the Cu and PdCu wire has led to the search of alternative bonding wire materials in which silver (Ag) or silver alloy wire (Ag alloy) has emerged as the preferred choice. Cu and PdCu wire induces a higher stress on the bond pad and underlying structure due to its inherent hardness value. Ag has similar mechanical properties as Au while it's cheaper and has higher thermal and electrical conductivity as compared to Au. When compared to Cu, Ag is similar in conductivity, but softer in terms of mechanical properties. The pure Ag bonding wire has some issues such as unstable free air ball (FAB) shape and poor reliability. To overcome these issues, alloyed Ag wire (Ag-Au-Pd) was developed and their FAB formation, bondability and reliability were studied. The package used is BGA type and the pad composition is Al-1%Si-0.5%Cu. Ag alloy wire delivers good and stable bonding capability using nitrogen as ambient gas. Both the bonded ball and stich bonding show good bond integrity. The reliability is determined by the high temperature storage life test (HTSL) test. Intermetallic compound (IMC) growth behavior during reliability test is characterized by the scanning electron microscopy (SEM) and energy dispersive spectrometer analyses (EDS). Two types of IMCs Ag2Al and Ag3Al were observed. No failure or voids are observed in the bulk IMC or metal-IMC interface after the HTSL test at 150C for 1000 hrs. Additionally these IMCs are fabricated in bulk and their resistivity and co-efficient of thermal expansion (CTE) properties are characterized to understand the likely source of failure of the Ag-Al bond. The CTE of the Ag3Al is lower than the Ag2Alwhich could be attributed to the lower stretching of lattice constant of former at higher temperature. The interface between the Al and Ag2Al is likely source of crack generation and failure because of the high CTE difference between them. The resistivity of the Ag3Al phase was found to slightly higher than Ag2Al. The information regarding the properties of Ag-Al IMCs are important for the finite element and quantum mechanics based first principle calculation and to ultimately predict their behavior in real life situation. The Ag alloy wire show floor life time of minimum 10 weeks based on bonded ball shape, workability and bondability test and there is no visible appreciable degradation of pull strength and bonded ball shape overtime. Ag alloy wire b","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128363001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lateral micro fluidic channels array chip fabrication for automated patch clamp application","authors":"Ding Zhipeng, Patthara Kongsuphol, Teh Poh Giao, Zhang Qingxin","doi":"10.1109/EPTC.2013.6745843","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745843","url":null,"abstract":"Traditionally, patch-clamp recording is accomplished with a micromanipulator-positioned glass pipette under a microscope. A cell membrane patch is sucked into the glass pipette and forms a high electrical resistance seal. The high cost and labor-intensive methods of conventional patch clamp have prevented the full potential of ion channels as a drug target class being fully realized. Automated patch clamp systems have recently been developed, in order to inexpensively collect large amounts of data in a shorter period of time. More common automation patch-clamp systems use microchips with tiny (1-2μm) holes in a plate instead of pipettes to create the gigaseals and record from single cells. In our previously reported works, a lateral aperture of a buried micro channel was demonstrated, which differs from the common planar patch aperture and is easier fluidic integration and packaging, higher-density array comparing with planar patch aperture. In this paper, we present the optimized fabrication process and integrated the optimized fabrication process to a new designed lateral patch-clamp array chip with 12 independent lateral patch-clamping sites for patch clamp application. At last, the new designed lateral patch clamp devices are utilized to conduct whole cell patch clamp measurements in rat insulinoma (INS-1) cells. High gigaseals (>1 GΩ) were formed between the glass capillary apertures and INS-1 cells. Steady state I-V plots elicited characteristic ion channel properties and longevity of the whole cell mode could be maintained for 1 h without any breakage of the gigaseals, which long enough to apply various compounds and ion channel drugs.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134372677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stress analysis of Si lattice near TSV structures","authors":"K. Chui, Zhaohui Chen, G. R. Wong, L. Ding, Mingbin Yu, Xiaowu Zhang, P. Lo","doi":"10.1109/EPTC.2013.6745828","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745828","url":null,"abstract":"As a result of differences in coefficient of thermal expansion (CTE), Cu-filled TSV induces strain in the Si lattice surrounding it. Strain can have significant impact on the electrical performance of the logic transistors. Therefore, it is essential to investigate the induced strain in the Si lattice around TSV structures. Conventional strain characterization techniques are only able to detect strain at micron-level resolutions. In this work, we demonstrated the use of HRTEM to extract the lateral and vertical strain profile in the Si lattice around the TSV with a detection resolution of 10nm. This serves to provide more detailed information on the strain profiles within the close vicinity (<;100nm) of the TSVs as their dimensions are scaled beyond the micron-regime.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133159726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bare copper and palladium coated copper wire chip to chip bonding feasibility study","authors":"O. Ho, L. Ying, Gan Pei Se","doi":"10.1109/EPTC.2013.6745709","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745709","url":null,"abstract":"Chip to chip Cu wire bonding studies have been carried out on TSLP package, with bare Cu and palladium coated copper (PCC) wire. This paper discusses on feasibility studies of Cu wire chip to chip bonding which include bump cut mode, scale lead setting and Cu bump oxidation risk assessment. From the results, it is shown that bump cut mode has significant effect to bonding results. Appropriate bump cut mode has to be selected for PCC wire in order to have a palladium coating on the bump cut surface. The PCC wire stitch pull is higher than bare Cu wire at both 0 hour and HTS168hours (200°C). Nevertheless, scale lead setting for stitch bond positioning is crucial to obtain optimum stitch bond length on bump, also avoid bonding at bump edge and wire short die. Evaluation on bump oxidation was also carried out to study the effect of Cu bump oxidation to stitch-bump interface. It is observed that higher Oxygen content on Cu bump after heat staging more than 5s without N2 gas protection. Void line is observed between stitch-bump interface for both 5s and 60s heat staging sample. No void line observed for PCC wire up to 60s heat staging. Void line between stitch-bump interface is further studied with HTS168hrs (200°C) and HTS500hrs (175°C) for void growth. Not degradation of stitch pull readings and void growth is observed.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":" 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132125335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"“Front-end-ization” of the back-end","authors":"Rajiv Roy","doi":"10.4071/isom-2013-THP13","DOIUrl":"https://doi.org/10.4071/isom-2013-THP13","url":null,"abstract":"The trend towards 3D stacking and Cu Pillar bumping has significantly altered the requirements for manufacturing tools in the back-end. Techniques and processes are beginning to resemble the front-end of 20 years ago but with updated and more affordable cost-of ownership capabilities. As an example, steppers would have been unheard of in the back-end. Today steppers are critical to achieve yield for devices ranging from fan-out wafer level chip scale packaging to Cu Pillar bumping. Re-distribution layer pitch has shrunk dramatically over the last few years, customers are demanding less than 5μm spacing and 5μm width. It is impossible to maintain effective CD over a 300mm wafer without a stepper on a three layer process. On wafer requirements, 0.5μm resolution inspection was state of the art 25 years ago. Today, fine pitch Cu Pillar is driving inspection of Cu bumps at similar resolution but at a significantly higher throughput and a much lower Cost-of-ownership (COO). Other traditional Front-end capabilities such as Metrology and Advanced Process Control (APC) that are being adopted by the back-end will also be discussed.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123890771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Solder joint structure and reliability of board level BGA package using no-clean curable solder paste","authors":"Choi Han, Jung Eunteak, Lee Sojung, Bang Junghwan, Kim， Junki","doi":"10.1109/EPTC.2013.6745711","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745711","url":null,"abstract":"In the SMT(surface mount technology) process, the cleaning process of flux residue is getting difficult due to the decrease of interconnection pitch. In this study, the curable type no-clean solder paste containing resin instead of rosin was formulated and its effectiveness on the reflow process accessibility and the thermal cycling and dynamic bending reliabilities were evaluated for the board level ball grid array package. It was found out that the solder joint and cured adhesive fillet could be properly formed after reflow process. The flux was cross-linked with epoxy resin to form the thermoplastic cured product. Although the formation of cured adhesive fillet at the only bottom side of solder joint seemed to be detrimental to the dynamic bending reliability, it was considered to be helpful to the thermal cycling reliability due to the reinforcement of ball and die shear strength.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124532653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Technology for bipolar polycarbonate electrodes applied for intraoperative neuromonitoring","authors":"M. Varga, M. Luniak, K. Wolter","doi":"10.1109/EPTC.2013.6745693","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745693","url":null,"abstract":"The paper presents a novel bipolar electrode for continuous evaluation and identification of neural dysfunction. The hook-up design realized with a careful choice of biocompatible materials, enhances the easy of implantation and positioning of the electrode during the medical procedure. In this regard, the proposed electrode offers a promising alternative for applications in neural electrical stimulation and recording.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129366450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Demonstration of OSAT compatible 300 mm through Si interposer","authors":"L. Ding, L. Liew, G. Lau, Hongyu Li, Mingbin Yu, G. Lo","doi":"10.1109/EPTC.2013.6745757","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745757","url":null,"abstract":"We demonstrated fine pitch TSV interposer (TSI) with OSAT-only infra-structure. This provides an alternative commercial worth technology path given that OSAT can also offer a turnkey solution making 300 mm fine pitch TSV interposer. A comprehensive fabrication and characterization has been presented for process modules, integration, and fabricated interposers.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129265024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Experiment and modeling of microstructured capillary wicks for thermal management of electronics","authors":"Qian Liang, R. Raj, S. Adera, S. Somasundaram, C. S. Tan, E. Wang","doi":"10.1109/EPTC.2013.6745789","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745789","url":null,"abstract":"Novel thermal management approaches are desired due to the ever-increasing power densities in high-performance microelectronics. The rising power density along with the shrinking real estate in these devices results in a substantial increase in device temperature beyond the typical operating temperatures required for a reliable performance. For the typical silicon based technology, efficient thermal management schemes with high heat transfer coefficients such that heat fluxes in excess of ≈ 100 W / cm2 can be dissipated without severely exceeding normal operating temperatures of ≈ 80°C are desired. State-of-the-art single phase cooling technologies that rely on sensible heat are bulky and insufficient under these conditions. As a result, liquid-vapor phase change based novel thermal management solutions which utilize latent heat of vaporization of a fluid for high heat transfer with little temperature increase are needed. In this work, we present a multiphase thermal management scheme where we use arrays of cylindrical micropillars of silicon for thin-film evaporation. The microstructures maintain a continuous liquid supply via capillary pressure while controlling the liquid film thickness and the associated thermal resistance. A variety of silicon samples with various wick geometries were fabricated using standard contact photolithography and deep reactive ion etching. Effects of micropillar diameter, pitch, height and the array length on the maximum heat dissipation capability before dry-out were investigated. An analytical model was developed to predict the experimentally observed values of the evaporative heat flux. While the parametric effects of micropillar geometry were qualitatively captured by the model predictions, quantitative predictions could not be achieved due to the limitations in the experimental setup. These preliminary results suggest the potential of thin-film evaporation on microstructured surfaces for advanced thermal management applications.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115662851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Clarification of stress field measured by multi-wavelength micro-raman spectroscopy in the surrounding silicon of copper-filled through-silicon vias (tsvs)","authors":"Y. S. Chan, Xiaowu Zhang","doi":"10.1109/EPTC.2013.6745791","DOIUrl":"https://doi.org/10.1109/EPTC.2013.6745791","url":null,"abstract":"Recently, micro-Raman spectroscopy has become popular in the near-surface silicon stress measurement around copper-filled through-silicon vias (TSVs). Since the stress σ_Raman measured by the micro-Raman spectroscopy is a combined result of all of the stress components, interpretation of this stress becomes obscure. Ryu et al. has claimed that σ_Raman is approximately biaxial and hence it is proportional to σ_r + σ_θ On the other hand, Wilson et al. has claimed that σ_r+σ_θ should be close to zero and hence σ_Raman is directly proportional to σ_z. In view of the dilemma as proposed by different research groups, this study aims to provide insight into the origin of this stress so that it can be understood and utilized properly.","PeriodicalId":210691,"journal":{"name":"2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127583026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}