Bare copper and palladium coated copper wire chip to chip bonding feasibility study

Abstract

Chip to chip Cu wire bonding studies have been carried out on TSLP package, with bare Cu and palladium coated copper (PCC) wire. This paper discusses on feasibility studies of Cu wire chip to chip bonding which include bump cut mode, scale lead setting and Cu bump oxidation risk assessment. From the results, it is shown that bump cut mode has significant effect to bonding results. Appropriate bump cut mode has to be selected for PCC wire in order to have a palladium coating on the bump cut surface. The PCC wire stitch pull is higher than bare Cu wire at both 0 hour and HTS168hours (200°C). Nevertheless, scale lead setting for stitch bond positioning is crucial to obtain optimum stitch bond length on bump, also avoid bonding at bump edge and wire short die. Evaluation on bump oxidation was also carried out to study the effect of Cu bump oxidation to stitch-bump interface. It is observed that higher Oxygen content on Cu bump after heat staging more than 5s without N2 gas protection. Void line is observed between stitch-bump interface for both 5s and 60s heat staging sample. No void line observed for PCC wire up to 60s heat staging. Void line between stitch-bump interface is further studied with HTS168hrs (200°C) and HTS500hrs (175°C) for void growth. Not degradation of stitch pull readings and void growth is observed.