Simultaneous molding and under-filling for void free process to encapsulate fine pitch micro bump interconnections of chip-to-wafer (C2W) bonding in wafer level packaging

Dexter Velez Sorono, S. Vempati, L. Bu, S. Chong, C.T.W. Liang, Seit Wen Wei
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引用次数: 6

Abstract

The encapsulation of chips with fine pitch micro bump interconnections in chip-to-wafer (C2W) bonding has a known two steps process in wafer level packaging. First step is underfilling process that fills the gap between bumps underneath the chips. Under-filling process can either be using liquid dispensing which allow it to flow underneath the bumped chips by capillary force or using a non-flow under-fill material. The second step is molding process that encapsulates the entire C2W with a molding compound. Through simultaneous molding and under-filling process to encapsulate, the two steps will become a single step process. Although, this method has been widely used for flip-chip Ball Grid Array (BGA) packaging using Moldable Under-fill (MUF) material in transfer molding, it is not yet fully utilized for wafer level C2W packaging using MUF material in wafer level compression molding. One major challenge during under-filling is voids formation underneath the bumped chips as shown in Fig. 1. This study aims to implement simultaneous molding and under-filling to achieve a void free process in wafer level C2W packaging. Mold flow simulation using ANSYS FLUENT 14.5 commercial software is being used to predetermine the major factors affecting the voids formation. Based on the simulation result, we have identified several factors that can significantly affect the voids size. The identified factors are mold temperature, mold compound dispensing pattern and mold filling speed. The mold flow simulation results are being validated using test chips with 90um micro bump pitch in the actual molding experiment. We validated the actual void formation by comparing the result of low and high molding temperature, comparing round and straight line dispensing pattern and also validated the use of slower filling speed during molding process. The experimental result confirms the total elimination of voids formation during simultaneous molding and under-filling process. The experimental result indicates that the actual molding perfectly match with the mold flow simulation result.
在晶圆级封装中,采用无空隙同时成型和欠填充工艺,封装芯片到晶圆(C2W)键合的细间距微凹凸互连
芯片到晶圆(C2W)键合中具有细间距微凸点互连的芯片封装在晶圆级封装中有两个已知的步骤。第一步是填充过程,填充芯片下面凸起之间的空隙。下填充过程可以使用液体点胶,使其通过毛细管力在凸起的芯片下流动,也可以使用不流动的下填充材料。第二步是成型过程,用成型化合物封装整个C2W。通过同时成型和下填充工序进行封装,两步工序将成为单步工序。虽然该方法已被广泛应用于倒装芯片球栅阵列(BGA)封装中,在传递成型中使用可塑下填充(MUF)材料,但尚未充分利用它在晶圆级C2W封装中使用MUF材料进行晶圆级压缩成型。如图1所示,充填过程中的一个主要挑战是在凸起的晶片下方形成空隙。本研究的目的是在晶圆级C2W封装中实现同时成型和欠填充,以实现无空隙工艺。利用ANSYS FLUENT 14.5商业软件进行模流模拟,预先确定影响孔洞形成的主要因素。根据模拟结果,我们确定了几个可以显著影响空隙尺寸的因素。确定的影响因素有模具温度、模具复合点胶方式和模具填充速度。在实际成型实验中,使用微凸距为90um的测试芯片对模流模拟结果进行了验证。我们通过比较低和高成型温度的结果,比较圆形和直线点胶模式来验证实际的空隙形成,并验证在成型过程中使用较慢的填充速度。实验结果证实,在同时成型和欠填充过程中完全消除了空洞的形成。实验结果表明,实际成型与模流仿真结果吻合较好。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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