用于电源应用的嵌入式晶圆级LGA封装的热循环可靠性评估和增强

Yiyi Ma, K. Goh, Xueren Zhang, Yonggang Jin
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引用次数: 1

摘要

新兴的扇出嵌入式晶圆级BGA (eWLB)技术在I/ o增长、多芯片和系统集成方面具有极大的可行性和灵活性,与传统的同类产品(即扇入式WLP或BGA技术)相比,被认为是一种更有利的封装解决方案。不断增加的集成电路芯片功能和减少芯片尺寸的产品小型化的无情趋势导致了更少的芯片空间和强烈的散热。虽然eWLB技术已经很好地解决了与前者相关的布线问题,但其固有的降低收缩芯片的扩散热阻的有效性限制了其在低功耗器件中的应用。因此,Quad Flat No-Lead (QFN)通常是这些应用的首选封装技术,因为QFN是基于引线框架的封装,其在封装表面底部的暴露模垫提供热和电增强。外露的模垫不仅为PCB提供了有效的热路径,而且还通过导电的模贴材料实现了稳定的接地。为了弥补eWLB和QFN概念之间的差距,以保留两者的优势,意法半导体最近提出了一种类似QFN的eWLB封装,称为嵌入式晶圆级LGA (eWLL),具有低外形,高引脚数和出色的热电性能。本文通过有限元分析(FEA)初步研究了eWLL封装在板级加速热循环(ATC)试验下的焊点可靠性。然后进行了实验,以评估有限元模型的准确性。结果表明,有限元模拟预测结果与实际试验结果吻合较好。然后将验证的有限元模型扩展到研究广泛的设计变量对eWLL封装板级可靠性的影响。对数值分析结果进行了比较和详细讨论。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Thermal cycling reliability assessment and enhancement of embedded wafer level LGA packages for power applications
With great feasibility and flexibility for growing I/Os, multi-chips and system integration, the emerging fan-out embedded Wafer Level BGA (eWLB) technology is regarded as a much more favorable packaging solution compared with its traditional counterparts, i.e. fan-in WLP or BGA technology. The relentless trend of ever increasing integrated circuit chip functionality and decreasing chip dimensions for miniaturization of products have led to less chip real estate and intense heat dissipation. While eWLB technology has well addressed the routing problems associated with the former, its intrinsic ineffectiveness of reducing the spreading thermal resistance of the shrunk die has limited its application to low power devices. As a result, Quad Flat No-Lead (QFN) is often a packaging technology of choice for those applications as QFN is a lead frame based package which offers thermal and electrical enhancement with its exposed die pad on the bottom of the package surface. The exposed die pad not only provides an efficient heat path to the PCB, but also enables stable grounding with electrical connection through a conductive die attach material. To bridge the gap between the eWLB and QFN concept so that both of their advantages can be retained, STMicroelectronics has recently come up with a QFN-like eWLB package known as embedded wafer level LGA (eWLL) with low profile, high pin count and excellent thermal and electrical performance. This paper initially investigated the solder joint reliability of the eWLL packages under board level Accelerated Thermal Cycling (ATC) test through Finite Element Analysis (FEA). Experiments were then carried out to assess the accuracy of the FEA model. It was found that the predictions made by the FEA simulation correlated very well with the actual test results. The validated FEA model was then extended to study the effect of a wide range of design variables on the board level reliability of the eWLL packages. The results of the numerical analysis are compared and discussed in details.
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