Wang Yuanchun, Man Weidong, Lv Changzhi, L. Zhiguo, Guo Chunsheng, Li Fei
{"title":"Thermal analysis of DC/DC module","authors":"Wang Yuanchun, Man Weidong, Lv Changzhi, L. Zhiguo, Guo Chunsheng, Li Fei","doi":"10.1109/IPFA.2009.5232619","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232619","url":null,"abstract":"Ever-increasing DC/DC power density and peak temperature challenge its reliability and performance. Thermal simulation and analysis play a significant role in development of new generation of DC/DC package design. This paper presents an accurate and fast approach to simulate the thermal distribution of a DC/DC module. The thermal distribution is simulated with ANSYS, and verified by infrared thermal images. This made feasible the thermal design to reduce stressing temperature peaks, so improving DC/DC reliability significantly.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130152893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chih-Hung Sun, Jyi-Tsong Lin, Y. Eng, Tzu-Feng Chang, Po-Hsieh Lin, Hsuan-Hsu Chen, C. Kuo, Hsien-Nan Chiu
{"title":"Advanced block oxide MOSFETs for 25 nm technology node","authors":"Chih-Hung Sun, Jyi-Tsong Lin, Y. Eng, Tzu-Feng Chang, Po-Hsieh Lin, Hsuan-Hsu Chen, C. Kuo, Hsien-Nan Chiu","doi":"10.1109/IPFA.2009.5232673","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232673","url":null,"abstract":"This paper proposes two ultimate block oxide (BO) devices called MOS with BO (bMOS) and middle partial insulation with BO (bMPI), respectively. Both he fabrications of the two devices are simple and self-alignment, which help to attain low-cost mass production. The bMOS shows better thermal stability than the bMPI because of its multiple-tie scheme. Also the most conspicuous one is the lattice temperature; bMOS shows about 40% lower temperature compared with the bMPI. However, the bMPI can gain better short-channel behavior due to the BOX under its channel layer. In addition, although the drain on-state current of the bMPI is lower than that of the bMOS, the lower leakage current helps to gain a higher ION/IOFF ratio. It is a trade-off between performance and reliability. Additionally, if the fabrication cost is also considered, the bMOS will exhibit better advantage than the bMPI because of a bulk wafer being used for a starting substrate.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130443530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Guoguang, Huang Yun, En Yunfei, Yang Shaohua, Lei Zhifeng
{"title":"Reliability of high power QCW cm-bar arrays","authors":"L. Guoguang, Huang Yun, En Yunfei, Yang Shaohua, Lei Zhifeng","doi":"10.1109/IPFA.2009.5232648","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232648","url":null,"abstract":"We report here the lifetime testing of 10 high power cm-bar arrays using an automated diode array reliability experiment. The devices are tested at 25°C/100A, with a pulse width of 200µs and a duty factor of 2%. Most devices survive more than 1.0×109 shots. Failure analysis results on the few failing devices reveal failure modes of mechanical stress, chemical contamination and thermal migration.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129806250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Z. Tao, Hong-Xia Liu, Qianwei Kuang, Nai-Qiong Cai, H. Yue, Zhao Aaron, Tallavarjula Sai
{"title":"Physical and structural properties of HfO2/SiO2 gate stack high-k dielectrics deposited by atomic layer deposition","authors":"Z. Tao, Hong-Xia Liu, Qianwei Kuang, Nai-Qiong Cai, H. Yue, Zhao Aaron, Tallavarjula Sai","doi":"10.1109/IPFA.2009.5232575","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232575","url":null,"abstract":"The ultra-thin HfO<inf>2</inf>/SiO<inf>2</inf> gate stack high-k dielectrics were deposited by Atomic Layer Deposition. The physical and structural properties of the HfO<inf>2</inf>/SiO<inf>2</inf> films were investigated. Atomic force microscopy, transmission electron microscopy and x-ray reflectivity analysis results indicate that the atomic layer deposition can deposit HfO<inf>2</inf>/SiO<inf>2</inf> gate stack dielectrics with good performance.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124392165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Huo, K. Ding, Y. Han, S. Dong, X.Y. Du, D. Huang, B. Song
{"title":"Effects of process variation on turn-on voltages of a multi-finger gate-coupled NMOS ESD protection device","authors":"M. Huo, K. Ding, Y. Han, S. Dong, X.Y. Du, D. Huang, B. Song","doi":"10.1109/IPFA.2009.5232711","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232711","url":null,"abstract":"The popular electrostatic discharge (ESD) protection device, multi-finger NMOS with gate-coupling technique for better uniform turning-on, can be affected by process variation. The transmission line pulsing (TLP) test results reveal this phenomenon. The trigger voltage of the same pin on some products shifts from 9.5V to 15.5V. No such significant difference was ever reported in the literature. In this study, the circuit simulations at various process corners are applied to study the snapback device under this situation. With only the NMOS gate-drain overlap as coupling capacitance, the gate-to-ground resistor plays a vital role in counteracting the variation. When increased from 3KOhm to 12KOhm, the turn-on voltage is reduced and the target ESD performance is achieved. The protection structure is processed on an EEPROM process, which is used as both I/O protection circuit and power-clamp. It is able to pass 4KV HBM ESD level.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122559064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S.J. Cho, T.E. Kim, J.K. Hong, J.T. Hong, H. Kim, Y.W. Han, S. Kwon, Y. Oh
{"title":"Logic failure analysis 65/45nm device using RCI & nano scale probe","authors":"S.J. Cho, T.E. Kim, J.K. Hong, J.T. Hong, H. Kim, Y.W. Han, S. Kwon, Y. Oh","doi":"10.1109/IPFA.2009.5232699","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232699","url":null,"abstract":"Scan chain failure analysis is more difficult and complicated compared to memory analysis and analysis of defect monitoring test element group (DTEG) which has a large area is also difficult. This paper has verified that various defects of logic process sub 65nm device are easily analyzed through Resistive Contrast Imaging (RCI) and nanoprobe. In addition, Metal5 (M5) bridge defect (Short case) was detected in failure of scan ATPG (Automatic Test Pattern Generation) which has long failing nets and by discovering Via4 (V4) open defect (Open case) by Unetch, it was confirmed that it is possible to analyze high resistance Via failure. And it was verified that position of Cu line void of metal7 (M7) can be localized at high level metal layer. It is judged that it will be used usefully in failure analysis sub 65nm in the future as a technique utilizing principle of RCI and nanoprobe and also it will make lots of contributions to improvement of yield.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"519 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123204929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Toh, P. K. Tan, E. Hendarto, Q. Deng, H. Lin, Y. W. Goh, L. Zhu, H. Tan, Q.F. Wang, R. He, J. Lam, L. Hsia, Z. Mai
{"title":"Electrical characteristics of leakage issues caused by defective Ni salicide","authors":"S. Toh, P. K. Tan, E. Hendarto, Q. Deng, H. Lin, Y. W. Goh, L. Zhu, H. Tan, Q.F. Wang, R. He, J. Lam, L. Hsia, Z. Mai","doi":"10.1109/IPFA.2009.5232669","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232669","url":null,"abstract":"Ni diffusion in sub-100 nm devices can adversely affect electrical performance, and contribute greatly to yield loss. Despite the tremendous advantages of Ni salicide technology over Ti or Co, there are problems associated with the intrinsic properties of NiSi. Ni spiking into Si substrate or conductive bridges between silicide on the gate electrodes and that on the source/drain terminals can occur. These effects can be induced or enhanced by stringent layout, stress or process conditions. Its impact can be evident from electrical failure analysis such as nanoprobing and C-AFM, that are useful in identifying the cause of failure.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115835294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Current topics on PV module and system reliability","authors":"L. Ji","doi":"10.1109/IPFA.2009.5232564","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232564","url":null,"abstract":"This presentation gives a brief introduction for current topics discussed in Photovoltaics (PV) industry, especially by the international standard, testing and certification community. So far, the widely used standards are either deal with a design qualification and type approval (such as IEC 61215, IEC 61646), or module safety (such as IEC 61730, UL 1703). Some people in the PV community considered, or declared, that if the product passed these test, they are guaranteed for 20 years or more operation. These opinions are considered by many experts as not correct. For example, on IEC 61215, it specified that “The object of this test sequence is to determine the electrical and thermal characteristics of the module and to show, as far as is possible within reasonable constraints of cost and time, that the module is capable of withstanding prolonged exposure in climates described in the scope. The actual lifetime expectancy of modules so qualified will depend on their design, their environment and the conditions under which they are operated.” The presentation includes newly founded failures occurred on the real PV installations, their possible failure roots, suggested corrections, modifications on standard requirements and testing methods. In specific, the hot-spot endurance test, salt mist test, long term polymer material test, and UV exposal test will be discussed in details.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128600997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Deyine, K. Sanchez, P. Perdu, F. Bourcier, F. Battistella, F. Bereil, P. Le Nouy, D. Lewis, H. Deslandes
{"title":"Full Dynamic Laser simulation set up","authors":"A. Deyine, K. Sanchez, P. Perdu, F. Bourcier, F. Battistella, F. Bereil, P. Le Nouy, D. Lewis, H. Deslandes","doi":"10.1109/IPFA.2009.5232665","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232665","url":null,"abstract":"Laser Stimulation techniques are continuously developed in accordance with the apparition of new kind of defect. We propose the Full Dynamic La-ser Stimulation where the test is fully embedded in the localization process. By using a modulated laser instead of a continuous one we discriminate vectors fail in ad-dition to localization.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125407525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. He, Jun Wang, Zhiming Wu, Yadong Jiang, K. Yuan
{"title":"Analysis of alignment modeling for Nikon steppers","authors":"F. He, Jun Wang, Zhiming Wu, Yadong Jiang, K. Yuan","doi":"10.1109/IPFA.2009.5232634","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232634","url":null,"abstract":"The alignment system, as one of key component for stepper, developed rapidly in the last few years because of huge requirement on advanced exposing tools for VLSI and MEMS. Alignment accuracy is mainly affected by errors coming from mark deformations and optical system. In this paper, we combined mathematical model of Nikon stepper alignment optical system and analyzed alignment errors of Nikon stepper caused by mark deformation in different processes. The model was verified by different experiments. Finally some improvement process is put forward to enhance alignment accuracy.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126767659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}