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2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits最新文献

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Thermal conductivity studies of a GaN-sapphire structure by combined scanning thermal microscopy and electron backscatter diffraction 用扫描热显微镜和电子背散射衍射联合研究gan -蓝宝石结构的热导率
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232593
Y. Zhang, L. Wang, Y. Ji, X. Han, Z. Zhang, R. Heiderhoff, A.-K. Tiedemann, L. Balk
{"title":"Thermal conductivity studies of a GaN-sapphire structure by combined scanning thermal microscopy and electron backscatter diffraction","authors":"Y. Zhang, L. Wang, Y. Ji, X. Han, Z. Zhang, R. Heiderhoff, A.-K. Tiedemann, L. Balk","doi":"10.1109/IPFA.2009.5232593","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232593","url":null,"abstract":"Scanning thermal microscope (SThM) and electron backscatter diffraction (EBSD) techniques were used to investigate the local thermal-conductivity of a GaN-buffer-sapphire heterostructure. Compared with GaN epilayer, buffer layer displayed the low thermal-conductivity and the high strain state due to the lattice distortion.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128218640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Thermal and bias stabilities of InP/InGaAs composite-collector DHBT InP/InGaAs复合捕集剂DHBT的热稳定性和偏置稳定性
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232643
Y. S. Lin, Y. Jou
{"title":"Thermal and bias stabilities of InP/InGaAs composite-collector DHBT","authors":"Y. S. Lin, Y. Jou","doi":"10.1109/IPFA.2009.5232643","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232643","url":null,"abstract":"This study proposes composite-collector double heterojunction bipolar transistors (CC-DHBTs) made by low-pressure metamorphic organic chemical vapor deposition (LP-MOCVD). Both V-shaped behaviors (observed in dc current gain, β, against collector current, I<inf>C</inf>, and in offset voltage, V<inf>CE,offset</inf>, against base current, I<inf>B</inf>, plot) of the asymmetric CC-DHBT are studied. At high I<inf>C</inf>, the presented CC-DHBTs improve the dc current gain temperature stability relative to most HBTs described in the literature. Additionally, unlike that of the abrupt DHBTs in the literature, the β of the CC-DHBTs is independent of V<inf>CB</inf>, suggesting that the effect of the conduction-band barrier in the base-collector junctions may haven been eliminated. An analytical expression for the variation of V<inf>CE,offset</inf> with I<inf>B</inf> has been developed. Additionally, unlike that of the unpassivated and SiN<inf>x</inf>-passivated devices, the β of the sulfur-treated device is fairly constant over five decades of I<inf>C</inf>. The difference betreen these variously treated devices is remarkable. X-ray photoelectron spectroscopy was applied to study InGaAs surfaces that were (NH<inf>4</inf>)<inf>2</inf>S<inf>x</inf> and SiN<inf>x</inf> passivated. The results demonstrate that passivation effectively suppresses the oxidation of As.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134356499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparison of charge trapping in silicon dioxide and hafnium dioxide at nanoscale 纳米尺度下二氧化硅和二氧化铪电荷俘获的比较
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232693
You-Lin Wu, Chiung-Yi Huang, Jing-Jenn Lin
{"title":"Comparison of charge trapping in silicon dioxide and hafnium dioxide at nanoscale","authors":"You-Lin Wu, Chiung-Yi Huang, Jing-Jenn Lin","doi":"10.1109/IPFA.2009.5232693","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232693","url":null,"abstract":"In this paper, we report a new measurement technique that can be used to determine the nanoscale charge trapping properties of gate oxide. Forward and backward sweep ramped voltage were applied to the samples in order to measure the nanoscale I–V characteristics using conductive atomic force microscopy (CAFM) in conjunction with a semiconductor parameter analyzer, Agilent 4156C. From the voltage hysteresis between the forward and backward sweeps I–V characteristics at a fixed current level, we successfully compared the differences between the nanoscale charge trapping in thermal SiO2 and ALD HfO2 gate dielectrics.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"90 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134093905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The effect of microstructure on electromigration induced voids 微观结构对电迁移诱导空洞的影响
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232556
H. Ceric, R. Orio, J. Červenka, Siegfried Selberherr
{"title":"The effect of microstructure on electromigration induced voids","authors":"H. Ceric, R. Orio, J. Červenka, Siegfried Selberherr","doi":"10.1109/IPFA.2009.5232556","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232556","url":null,"abstract":"We present the application of a state of the art electromigration model on a dual damascene interconnect with typical copper microstructure. The influence of the microstructure on the formation and development of an electromigration induced void is studied by simulation and the results are compared with experiments. A close investigation has shown that the network of grain boundaries has a decisive impact on the formation of void nucleation sites and void development.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126998501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Radiation hardened read circuit with high reliability for SOI based SONOS memory 基于SOI的SONOS存储器的高可靠性防辐射读电路
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232661
Kan Li, Dong Wu, Xueqian Wang, Fengying Qiao, Ning Deng, L. Pan
{"title":"Radiation hardened read circuit with high reliability for SOI based SONOS memory","authors":"Kan Li, Dong Wu, Xueqian Wang, Fengying Qiao, Ning Deng, L. Pan","doi":"10.1109/IPFA.2009.5232661","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232661","url":null,"abstract":"A radiation hardened read circuit for a SONOS type EEPROM memory is designed in 0.6µm SOI process. Total dose radiation would cause large threshold voltage shifts of both memory cells and MOS transistors, hence degrades the reliability and performance of the sense amplifier. Compensation techniques for the sampling inverter and discharge path are proposed to achieve radiation hardness. Double branch precharge technique is developed to improve the read speed. As a result, the proposed sense amplifier is not sensitive to the radiation. Besides its high reliability, the proposed read circuit demonstrates high speed, achieving a sensing time of only 9.67ns.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122029506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis and experiment of surface bending to grating light modulator 光栅光调制器表面弯曲的分析与实验
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232639
Lin Shi, Yingjin Pan, Zhihai Zhang, Jie Zhang, Weiwei, Wei Wang
{"title":"Analysis and experiment of surface bending to grating light modulator","authors":"Lin Shi, Yingjin Pan, Zhihai Zhang, Jie Zhang, Weiwei, Wei Wang","doi":"10.1109/IPFA.2009.5232639","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232639","url":null,"abstract":"The effects of diffraction characteristics that the surface bending to two dimension grating light modulators is discussed in this paper. With consideration of surface bending, a corresponding model is built based on experimental data, and then the effects of different bending to the modulation results have been calculated which is testified by experiments.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124974402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Chip package interaction (CPI) reliability of Cu/low-k/ultra-low-k interconnect Cu/低k/超低k互连的芯片封装交互(CPI)可靠性
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232555
Lei Fu, Michael Su, F. Kuechenmeister, Weidong Huang
{"title":"Chip package interaction (CPI) reliability of Cu/low-k/ultra-low-k interconnect","authors":"Lei Fu, Michael Su, F. Kuechenmeister, Weidong Huang","doi":"10.1109/IPFA.2009.5232555","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232555","url":null,"abstract":"The introduction of low-k/ultra-low-k (ULK) dielectric materials to accommodate the continuous scaling down of the feature sizes of IC chips to improve the device density and performance of the ultra-large scale integrated (ULSI) circuits represents great silicon and packaging integration challenges due to the weak mechanical properties. To improve CPI reliability of Cu/low-k or ULK devices, a new crackstop design has been introduced. Underfill materials selection, ULK layer effect, interfacial strength improvement of low-k/ULK films, and lead-free impact on chip-package interaction (CPI) reliability are also discussed.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123951963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Effect of metal routing on the ESD robustness of dual-direction silicon controlled rectifier 金属走线对双向可控硅ESD稳健性的影响
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232637
W. Guo, Mingliang Li, S. Dong
{"title":"Effect of metal routing on the ESD robustness of dual-direction silicon controlled rectifier","authors":"W. Guo, Mingliang Li, S. Dong","doi":"10.1109/IPFA.2009.5232637","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232637","url":null,"abstract":"Effect of metal routing on the robustness of silicon controlled rectifier (SCR) is studied for bi-direction electrostatic discharge (ESD) protection applications. Depending on the type of metal routing, different failure currents It2 can exist in the positive and negative directions due to the asymmetrical current conductions in the multi-finger dual-direction SCR. Transmission line pulsing (TLP) results are included in support of the analysis.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130074457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Self-aligned SOI MOSFETs with Ω-shaped conductive layer and source/drain-tie 具有Ω-shaped导电层和源/漏极结的自对准SOI mosfet
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232558
Jyi-Tsong Lin, Tzu-Feng Chang, Y. Eng, Hsuan-Hsu Chen, C. Kuo, Chih-Hung Sun, Po-Hsieh Lin, Hsien-Nan Chiu
{"title":"Self-aligned SOI MOSFETs with Ω-shaped conductive layer and source/drain-tie","authors":"Jyi-Tsong Lin, Tzu-Feng Chang, Y. Eng, Hsuan-Hsu Chen, C. Kuo, Chih-Hung Sun, Po-Hsieh Lin, Hsien-Nan Chiu","doi":"10.1109/IPFA.2009.5232558","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232558","url":null,"abstract":"In this paper, we propose a novel self-aligned silicon-on-insulator (SOI) MOSFET with Ω-shaped conductive layer and source/drain-tie (SA-ΩCFET). Based on the TCAD 2D simulation results, we find that combining the applications of a nature Source/Drain (S/D) tie with a recessed S/D region can effectively improve the issue of self-heating effects, but without losing control of the short-channel effects. Moreover, owing to the presence of the thick S/D junction thickness the parasitic S/D series resistance is reduced thus our proposed structure can gain a higher drain on-current and a higher maximum transconductance as compared with the conventional UTSOI device.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127764947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Failure analysis overview and its new challenges 失效分析概述及其新挑战
2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2009-07-06 DOI: 10.1109/IPFA.2009.5232690
Susan X. Li
{"title":"Failure analysis overview and its new challenges","authors":"Susan X. Li","doi":"10.1109/IPFA.2009.5232690","DOIUrl":"https://doi.org/10.1109/IPFA.2009.5232690","url":null,"abstract":"Failure analysis is a critical step for solving design, process, product and customer application issues. Failure analysts need to have strong and broad technical background as well as unique personality to be successful in this field. Failure analysis flow contains 8 basic steps, and should be followed to ensure the quality of the daily analysis work. Three case studies were demonstrated on how to use the 8-step FA flow to solve real life problems. With new technology, device materials and architecture in advanced products, new challenges need to be met in order to successfully support the failure analysis needs in the coming years.","PeriodicalId":210619,"journal":{"name":"2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127795664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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