Effects of process variation on turn-on voltages of a multi-finger gate-coupled NMOS ESD protection device

Abstract

The popular electrostatic discharge (ESD) protection device, multi-finger NMOS with gate-coupling technique for better uniform turning-on, can be affected by process variation. The transmission line pulsing (TLP) test results reveal this phenomenon. The trigger voltage of the same pin on some products shifts from 9.5V to 15.5V. No such significant difference was ever reported in the literature. In this study, the circuit simulations at various process corners are applied to study the snapback device under this situation. With only the NMOS gate-drain overlap as coupling capacitance, the gate-to-ground resistor plays a vital role in counteracting the variation. When increased from 3KOhm to 12KOhm, the turn-on voltage is reduced and the target ESD performance is achieved. The protection structure is processed on an EEPROM process, which is used as both I/O protection circuit and power-clamp. It is able to pass 4KV HBM ESD level.