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International Conference on Microelectronic Test Structures最新文献

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A new method to determine effective channel widths of MOS transistors for VLSI device design 为超大规模集成电路器件设计确定MOS晶体管有效沟道宽度的新方法
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67906
C. Wan, H. Yang, B. Sheu
{"title":"A new method to determine effective channel widths of MOS transistors for VLSI device design","authors":"C. Wan, H. Yang, B. Sheu","doi":"10.1109/ICMTS.1990.67906","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67906","url":null,"abstract":"A resistive method for determining the effective channel widths of MOS transistors is presented. In this method, the series resistance is determined using the channel-length characterization method. A practical approximation is used to calculate the series resistance for transistors with different channel widths. The test structure for this method consists of two sets of transistors: one set contains transistors with different channel lengths and the same channel width, and the other set contains transistors with different channel widths and the same channel length. Experimental results show that this method can be used with good accuracy when the series resistance is comparable to the channel resistance. The method is suitable for test structures with transistor channel-length in the submicrometer range.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123757464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The application of AI techniques to the control and interpretation of C-V measurements 人工智能技术在控制和解释C-V测量中的应用
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67904
J. Walls, A. Walton, J. Robertson
{"title":"The application of AI techniques to the control and interpretation of C-V measurements","authors":"J. Walls, A. Walton, J. Robertson","doi":"10.1109/ICMTS.1990.67904","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67904","url":null,"abstract":"Pattern-recognition and knowledge-based techniques are applied to help advance the interpretation of capacitance-voltage (C-V) curves. This is implemented by integrating instrument control software with an expert system shell to intelligently sequence tests to enhance conventional measurements. A prototype system is able to correctly identify a number of process faults, including a leaky oxide, as described in examples. In this instance some useful information could be obtained and a warning issued to the operator about the possible inaccuracy of some of the other parameters. Moreover, further analyses are disabled on account of the sample being inappropriate for their assumed equivalent circuit models. Other examples illustrate the improvements to be gained from measurements simply by recognizing the important factors in a single C-V measurement.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130196462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A parallel measurement system for the extraction of level 3 SPICE parameters 一种用于3级SPICE参数提取的平行测量系统
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67893
A. A. Walker, P. Touhy, A. Walton, J. Robertson
{"title":"A parallel measurement system for the extraction of level 3 SPICE parameters","authors":"A. A. Walker, P. Touhy, A. Walton, J. Robertson","doi":"10.1109/ICMTS.1990.67893","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67893","url":null,"abstract":"A fast and cost-efficient system to measure level-3 SPICE parameters is described. The extraction process takes 30 measurements in 18 measurement cycles using six MOSFETs and an oxide capacitor. Many of the measurements are performed in parallel and this significantly reduces the combined measurement and extraction time.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128688514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Defect size distribution in VLSI chips 超大规模集成电路芯片中的缺陷尺寸分布
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67880
R. Glang
{"title":"Defect size distribution in VLSI chips","authors":"R. Glang","doi":"10.1109/ICMTS.1990.67880","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67880","url":null,"abstract":"VLSI patterns consisting of parallel lines of polysilicon with different spacings have been electrically tested. The number of observed shorts was found to be related to the line spacings by using an analytical model for the defect sensitive pattern areas. The distribution of defect sizes in the range from 0.5 to 1.4 mu m is proportional to x/sup -3/. The exponent value agrees with earlier distribution studies concerning defects several micrometers in size.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117173490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
A crossbridge for measurement of gate-limited source/drain diffusion 用于测量栅限源/漏扩散的十字桥
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67886
M. A. Mitchell, C. Figura, L. Forner
{"title":"A crossbridge for measurement of gate-limited source/drain diffusion","authors":"M. A. Mitchell, C. Figura, L. Forner","doi":"10.1109/ICMTS.1990.67886","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67886","url":null,"abstract":"For self-aligned CMOS technology a test structure for measuring and controlling the electrical width of the source-drain diffusion, the gate-limited source drain crossbridge, and supporting electrical data is described. The results of the linewidth measurements are shown. The distribution of the difference between the polysilicon line spacing and the source-drain diffusion width is shown. A variation in source-drain diffusion width which is larger than the experimental error and not attributable only to the variation in polysilicon linewidth is detected. Additional factors which contribute to source-drain dimension variations are described.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114227856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Novel test structure to study junction leakage current 新颖的结漏电流测试结构
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67905
N. Koike, K. Tominaga
{"title":"Novel test structure to study junction leakage current","authors":"N. Koike, K. Tominaga","doi":"10.1109/ICMTS.1990.67905","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67905","url":null,"abstract":"A test structure for studying the junction leakage current independently of the additional leakage current induced by the process steps for the formation of the diffusion region under contacts is introduced. The test structures purpose is to evaluate the dynamic random access memory (DRAM) process in relation to the DRAM refresh time; it allows the junction leakage current in a certain voltage range, to be measured independently of the additional leakage current caused by the diffusion region under contacts. The structure is applied to the measurements in narrow diffusion regions, and it is shown that, the junction leakage current is induced mainly by local oxidation of silicon (LOCOS) oxide edge stress.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124136028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new test structure to characterize the latchup effect 一种新的测试结构来表征闭锁效应
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67878
C. Cané, M. Lozano, E. Cabruja, E. Lora-Tamayo, F. Serra-Mestres
{"title":"A new test structure to characterize the latchup effect","authors":"C. Cané, M. Lozano, E. Cabruja, E. Lora-Tamayo, F. Serra-Mestres","doi":"10.1109/ICMTS.1990.67878","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67878","url":null,"abstract":"A test structure for easily determining the sensitivity of different geometries and technological options to latchup is presented. The circuit is an astable oscillator composed of a p-n-p-n device with an integrated resistor and capacitor. It is used to obtain fast and comparative results with very simple instrumentation. Test structures are designed and produced with a 5- mu m CMOS process, although they are specially suited for VLSI technologies. Experimental results give very good agreement with other latchup test procedures. Much more accuracy can be obtained with a simple digital oscilloscope.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133248668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Yield modeling from SRAM failure analysis 基于SRAM失效分析的良率建模
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67898
H. Parks
{"title":"Yield modeling from SRAM failure analysis","authors":"H. Parks","doi":"10.1109/ICMTS.1990.67898","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67898","url":null,"abstract":"Yield models based on Poisson, bose-Einstein, and binomial statistics are compared for a 1.25 mu m CMOS process. A mixed binomial yield model is shown to most accurately describe experimental yield data for a 1.25- mu m CMOS process. The model consists of gross yield and random yield components based on gross and random defects determined on a per level basis from a static random access memory-test element group (SRAM-TEG) yield vehicle failure analysis. The random yield component consists of both binomial and negative binomial segments, hence the mixed terminology, depending on whether or not a given defect shows evidence of clustering. Simple negative binomial models become optimistic at larger chip sizes by ascribing too much importance to interlevel effects of defect clustering. Using defect size distributions measured on a per level basis, the model is shown to hold over chip variations in feature size, product type, and chip area.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115777434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Fault chip defect characterization for wafer scale integration 晶圆规模集成的故障芯片缺陷表征
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67882
D. Hannaman, H. Sayah, R. Allen, M. Buehler, M. Yung
{"title":"Fault chip defect characterization for wafer scale integration","authors":"D. Hannaman, H. Sayah, R. Allen, M. Buehler, M. Yung","doi":"10.1109/ICMTS.1990.67882","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67882","url":null,"abstract":"A fault chip was designed and fabricated on a 2- mu m CMOS wafer-scale integration (WSI) process with greater than 90% wafer coverage. The chip consists of pinhole array capacitors, serpentine resistors, and comb resistors. These structures are tailored to simulate the basic cell in the WSI circuit. Defect cluster analysis, using the negative binomial distribution, indicated that significant clustering occurs for a number of defect types and varies from wafer to wafer.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"271 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129051463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The spidermask: a new approach for yield monitoring using product adaptable test structures 蜘蛛罩:一种使用产品适应性测试结构进行产量监测的新方法
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67881
S. Beckers, C. Hiltrop
{"title":"The spidermask: a new approach for yield monitoring using product adaptable test structures","authors":"S. Beckers, C. Hiltrop","doi":"10.1109/ICMTS.1990.67881","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67881","url":null,"abstract":"An approach for yield monitoring based on a test vehicle that consists of structures, built on the underground of a high volume product is described. A specially designed metal mask, called spidermask, together with its appropriate contact mask, isolates and contacts these individual structures to create a complete yield monitor set. The major advantage of this type of structure is the close relationship between the measurement results on the test structure itself and the actual performance of the corresponding product. As a consequence, the existing yield model is adapted to conform to the yield monitor data. The spidermask was implemented in a CMOS and in a mixed bipolar-CMOS technology. The data of both yield monitors are presented, and the relationship with the yield model is demonstrated.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117004992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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