为超大规模集成电路器件设计确定MOS晶体管有效沟道宽度的新方法

C. Wan, H. Yang, B. Sheu
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引用次数: 0

摘要

提出了一种确定MOS晶体管有效沟道宽度的电阻法。该方法采用通道长度表征法确定串联电阻。用一个实用的近似方法计算了不同沟道宽度晶体管的串联电阻。该方法的测试结构由两组晶体管组成:一组包含不同通道长度和相同通道宽度的晶体管,另一组包含不同通道宽度和相同通道长度的晶体管。实验结果表明,当串联电阻与通道电阻相当时,该方法具有较好的精度。该方法适用于测试晶体管通道长度在亚微米范围内的结构。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A new method to determine effective channel widths of MOS transistors for VLSI device design
A resistive method for determining the effective channel widths of MOS transistors is presented. In this method, the series resistance is determined using the channel-length characterization method. A practical approximation is used to calculate the series resistance for transistors with different channel widths. The test structure for this method consists of two sets of transistors: one set contains transistors with different channel lengths and the same channel width, and the other set contains transistors with different channel widths and the same channel length. Experimental results show that this method can be used with good accuracy when the series resistance is comparable to the channel resistance. The method is suitable for test structures with transistor channel-length in the submicrometer range.<>
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