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International Conference on Microelectronic Test Structures最新文献

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Sources of error in electrical measurements of dimensional offset and sheet resistance in the near- and sub-micron region 近微米和亚微米区域尺寸偏移和薄片电阻电测量中的误差来源
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67887
J. Trager
{"title":"Sources of error in electrical measurements of dimensional offset and sheet resistance in the near- and sub-micron region","authors":"J. Trager","doi":"10.1109/ICMTS.1990.67887","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67887","url":null,"abstract":"The accuracy of the measurements of the sheet resistance and dimensional offsets for several conducting layers is investigated using various test structures with design widths ranging from 0.6 mu m to 32 mu m. Width-independence as well as electric field-dependence of the sheet resistance is found to be a main source of error. Different topography beneath resistor stripes and nonisotropic processing in the submicron region further affect the measurement results.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116719969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Self-multiplexing force-sense test structures for (MOS) IC applications 用于(MOS) IC应用的自复用力感测试结构
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67884
K.L.M. van der Klauw, J. Joosten, L. A. Wall
{"title":"Self-multiplexing force-sense test structures for (MOS) IC applications","authors":"K.L.M. van der Klauw, J. Joosten, L. A. Wall","doi":"10.1109/ICMTS.1990.67884","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67884","url":null,"abstract":"A self-multiplexing technique which enables multiple force-sense measurements to be carried out on test structures in the small area scribe lanes of product chips is presented. Instead of using separate address signals, the technique uses the distribution of stimulus and sense voltages across lines to select the proper test structure, drastically reducing the number of probe pads required. A simple, robust prototype circuit, which enables four independent test structures to be measured with only five probe pads, is presented. The technique can be extended to n(n-1) structures for n probe pads with some additional circuitry. Excellent measurement accuracy is obtained, and the circuit allows a wide range of operating conditions, remaining insensitive to process variations.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128486634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Investigation of self-heating in VLSI and ULSI MOSFETs VLSI和ULSI mosfet的自热研究
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67907
P.G. Mautry, J. Trager
{"title":"Investigation of self-heating in VLSI and ULSI MOSFETs","authors":"P.G. Mautry, J. Trager","doi":"10.1109/ICMTS.1990.67907","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67907","url":null,"abstract":"Temperature measurements both inside and near MOSFETs were taken using special test structures. At constant bias, the temperature rise normalized with respect to the dissipated power is found to be proportional to L/sup -1/2/, where L denotes the channel length. Source-drain asymmetries of the temperature distribution were detected. The temperature rise causes a fast reduction of channel conductivity, and is pronounced for short transistors. Numerical simulations reproduce the measured high speed of the temperature rise inside MOSFETs. It is enhanced for short-channel devices and leads to an underestimation of the speed of integrated circuits. In real devices, errors in modeling delay times may therefore arise causing jitter and skew between separate signal paths. As device dimensions further scale down and the self-heating effect increases, this must be considered and eventually corrected by using the characteristics of cold transistors.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132475422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
Reliability of latchup characterization procedures 闭锁表征程序的可靠性
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67879
W. Reczek, F. Bonner, B. Murphy
{"title":"Reliability of latchup characterization procedures","authors":"W. Reczek, F. Bonner, B. Murphy","doi":"10.1109/ICMTS.1990.67879","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67879","url":null,"abstract":"Three different well bias concepts are studied in detail under worst-case (power-on) conditions to evaluate the reliability of three distinct latchup characterization methods. An electrical method shows the most reliable results for the detection of latchup occurrence. A laser scanning method is the most reliable for localization of latchup susceptible regions. While the imaging of faint light is useful for detecting hot electrons and transistors in saturation, it is of little value for latchup observations.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122142616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Novel test structures for the investigation of the efficiency of guard rings used for I/O-latch-up prevention 用于防止I/ o闭锁保护环效率研究的新型试验结构
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67876
J. Quincke
{"title":"Novel test structures for the investigation of the efficiency of guard rings used for I/O-latch-up prevention","authors":"J. Quincke","doi":"10.1109/ICMTS.1990.67876","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67876","url":null,"abstract":"Test structures for guard ring efficiency measurements concerning input/output (I/O) latchup in integrated CMOS circuits for minority and majority carrier injection are introduced. The locations of two guard rings are varied for n/n/sup +/-epi (epitaxial) material and n-substrate. Latchup measurements were taken using a worst case detector, which simulates neighboring internal logic circuits. In non-epi material, the total efficiency of substrate guard rings for majority carrier injection, and of well guard rings for minority carrier injection is nearly equal (factor for the trigger current approximately=20). For epi material, the substrate guard rings for majority carrier injection have very little influence; but the trigger current without guard rings is already 25 times higher than for non-epi material.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128470896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Latch-up characterization in standard and twin-tub test structures by electrical measurements, 2-D simulations and IR microscopy 通过电测量、二维模拟和红外显微镜对标准和双桶测试结构的闭锁特性进行表征
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67877
T. Cavioni, M. Cecchetti, M. Muschitiello, G. Spiazzi, I. Vottre, E. Zanoni
{"title":"Latch-up characterization in standard and twin-tub test structures by electrical measurements, 2-D simulations and IR microscopy","authors":"T. Cavioni, M. Cecchetti, M. Muschitiello, G. Spiazzi, I. Vottre, E. Zanoni","doi":"10.1109/ICMTS.1990.67877","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67877","url":null,"abstract":"The influence of different layout parameters on latchup susceptibility was studied on standard four-stripes test structures fabricated using two bulk processes: standard n-well and a twin-tub technology. Twin-tub structures show increased latchup hardness and guard-ring effectiveness, mainly due to the increased doping level and the consequent decrease in substrate and well resistances. Standard and twin-tub structures show marked three-dimensional effects in the holding characteristics, which lead to an uneven distribution of the latchup current within test structures and hysteresis in the I-V characteristics.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131382509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Test structures and finite element models for chip stress and plastic package reliability 芯片应力和塑料封装可靠性的测试结构和有限元模型
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67896
R. Pendse, J. Demmin
{"title":"Test structures and finite element models for chip stress and plastic package reliability","authors":"R. Pendse, J. Demmin","doi":"10.1109/ICMTS.1990.67896","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67896","url":null,"abstract":"Failure modes induced by plastic package stress in multilayer metal-dielectric-passivation structures in large chips are investigated. An arrayable test chip is designed to contain representative metal-dielectric configurations that lend themselves to simple electrical measurement of stress-induced failures such as metal-to-metal leakage caused by interlayer dielectric cracking. Extensive data on the effects of chip size, distance from the corner, metal geometry, temperature cycling, and assembly variables are generated using the test chip. The failure modes are investigated using finite-element modeling (FEM). A modeling technique is used to address the problem of corner singularities, which is encountered in calculating shear stresses near chip corners. An approach is developed to derive die design rules using the accelerated failure rate data generated by the test chip in conjunction with the FEM stress curves. Some simple solutions to the package stress problem are demonstrated.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116102944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
On-chip quasi-static floating-gate capacitance measurement method 片上准静态浮栅电容测量方法
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67889
C. Kortekaas
{"title":"On-chip quasi-static floating-gate capacitance measurement method","authors":"C. Kortekaas","doi":"10.1109/ICMTS.1990.67889","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67889","url":null,"abstract":"An accurate interconnect capacitance parameter measurement technique is described. The technique is based on measurement of a capacitively divided DC voltage by means of a source follower stage integrated in the test structure. Determining of dielectric thickness as well as interconnect capacitance parameters using this technique in combination with special test patterns is described. The method shows good agreement with two-dimensional computer simulations. The technique is proven to be practical, reliable, and suited for use with manual and automatic parametric test equipment.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114707056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
New detection method of hot-carrier degradation using photon spectrum analysis of weak luminescence on CMOS VLSI 基于CMOS VLSI弱发光光子光谱分析的热载流子降解检测新方法
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67894
N. Tsutsu, Y. Uraoka, Y. Nakata, S. Akiyama, H. Esaki
{"title":"New detection method of hot-carrier degradation using photon spectrum analysis of weak luminescence on CMOS VLSI","authors":"N. Tsutsu, Y. Uraoka, Y. Nakata, S. Akiyama, H. Esaki","doi":"10.1109/ICMTS.1990.67894","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67894","url":null,"abstract":"A method developed to find the weakest transistor against hot-carrier-induced degradation by counting photon emission of various wavelengths in an operating VLSI circuit is presented. The method's underlying principle is that high-energy photons emitted from the transistors are caused by hot-carrier effects. The spectral distribution of photon energy emitted from n-channel MOSFETs is studied, and is found to follow the Maxwell-Boltzmann distribution. Photon emission with about 200 nm wavelength strongly correlates with hot-carrier-induced degradation. This method was applied to the static random access memory in a microprocessor. Transistors which are estimated to be seriously degraded by hot-carrier effect were detected. This method improves the reliability of VLSI circuits without long-term testing.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126368992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A practical method for extracting impurity profiles and effective mobilities of MOSFET's with nonuniform channel doping 一种提取非均匀沟道掺杂MOSFET的杂质分布和有效迁移率的实用方法
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67872
K. Kubota, Y. Kawashima, Y. Ohkura, M. Nagao
{"title":"A practical method for extracting impurity profiles and effective mobilities of MOSFET's with nonuniform channel doping","authors":"K. Kubota, Y. Kawashima, Y. Ohkura, M. Nagao","doi":"10.1109/ICMTS.1990.67872","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67872","url":null,"abstract":"Complete profiling of channel impurity concentration up to the surface is presented using Gaussians whose parameters are determined, giving optimum fits to the measured capacitance voltage (C-V) profiles. A rectangular capacitor with a large aspect ratio is found to be effective in reducing series resistance for accurate (C-V) measurements at high frequencies. Effective mobilities are extracted from practical MOSFETs based on numerical analysis of the field effects using the obtained profiles and compared to those for uniform doping.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"3 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123694988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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