International Conference on Microelectronic Test Structures最新文献

筛选
英文 中文
A novel approach for reducing the area occupied by contact pads on process control chips 一种减少过程控制芯片上触点片所占面积的新方法
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67883
A. Walton, W. Gammie, D. Morrow, J. Stevenson, R. Holwill
{"title":"A novel approach for reducing the area occupied by contact pads on process control chips","authors":"A. Walton, W. Gammie, D. Morrow, J. Stevenson, R. Holwill","doi":"10.1109/ICMTS.1990.67883","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67883","url":null,"abstract":"An approach which reduces the number of pads required by electrical test structures is presented. The multiplexed scheme requires only two levels of interconnect and enables more devices to be located in a given area, providing the designer of test structures with more freedom to experiment with structures previously requiring a large number of pads. Applications for transistors, electrical verniers, yield monitoring, reliability evaluations, continuity tests, and measuring the resistance of tracks are discussed.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124592763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Electrical characterization of 2-D doping profiles 二维掺杂谱的电特性
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67871
G. Ouwerling, J. Staalenburg, M. Kleefstra
{"title":"Electrical characterization of 2-D doping profiles","authors":"G. Ouwerling, J. Staalenburg, M. Kleefstra","doi":"10.1109/ICMTS.1990.67871","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67871","url":null,"abstract":"The extension of traditional electrical doping profiling methods, such as the capacitance-voltage (C-V) method, to two-dimensional doping profiling is discussed. Suitable test structures are proposed. The measurement data are interpreted with inverse modeling, which minimizes the difference between measured electrical data and measurement data simulated using a parameterized model of the doping profile. Experimental results are provided for the 2-D doping profile in the junction charge-coupled device (CCD). The application of the inverse modeling technique to device parameter extraction in a more general sense is briefly discussed.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122987310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new extraction method for effective channel length on lightly doped drain MOSFET's 轻掺杂漏极MOSFET有效沟道长度的新提取方法
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67890
J. Ida, A. Kita, F. Ichikawa
{"title":"A new extraction method for effective channel length on lightly doped drain MOSFET's","authors":"J. Ida, A. Kita, F. Ichikawa","doi":"10.1109/ICMTS.1990.67890","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67890","url":null,"abstract":"An extraction method for an effective channel length (L/sub eff/) on lightly doped drain (LDD) MOSFETs is proposed. In the method, the L/sub eff/ is obtained by the linear extrapolation of the gate-bias-dependent L/sub eff/ to the threshold voltage. In order to clear the difference of the gate bias dependence of the L/sub eff/ among various LDD structures, the LDDs are examined with experiments and simulations. The L/sub eff/ of LDDs corresponds to the metallurgical length. It is shown that MOSFET parameters can be reasonably characterized when the L/sub eff/ obtained by the method is used.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123331204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Test structure data classification using a directed graph approach 使用有向图方法测试结构数据分类
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67902
M. Cresswell, D. Khera, L. W. Linholm, C. E. Schuster
{"title":"Test structure data classification using a directed graph approach","authors":"M. Cresswell, D. Khera, L. W. Linholm, C. E. Schuster","doi":"10.1109/ICMTS.1990.67902","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67902","url":null,"abstract":"Directed graph techniques are introduced, serving as an expert system rule generator by classifying selections of tested wafers into groups based on similarities of the spatial distributions of their parametric test structure measurements. A self-normalizing equivalent vector inner product is devised to accommodate the ternary nature of the DC parametric test. It provides for test results that do not definitively pass a self-validation test. An algorithmic feature for avoiding special cases of nonoptimum search termination is conceived and implemented. The rules can be used to supplement those derived by other means of diagnostic process analysis, work-in-process wafer screening, and yield and reliability management.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129960862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Flange correction to four-terminal contact resistance measurements 四端接触电阻测量的法兰校正
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67875
U. Lieneweg, D. Hannaman
{"title":"Flange correction to four-terminal contact resistance measurements","authors":"U. Lieneweg, D. Hannaman","doi":"10.1109/ICMTS.1990.67875","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67875","url":null,"abstract":"A heuristic model for flange correction to four-terminal measurements of the interfacial resistance in square contacts between a semiconducting and a metal layer, or between metal layers is presented. The model reproduces results from experiments with geometric variations when a constant interfacial resistivity is fitted, and compares well to simulations.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128600805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Transmission line model test structure with four or more terminals: a novel method to characterize non-ideal planar ohmic contacts in presence of inhomogeneities 具有四个或更多端子的传输线模型测试结构:一种表征存在不均匀性的非理想平面欧姆接触的新方法
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67874
L. Gutai
{"title":"Transmission line model test structure with four or more terminals: a novel method to characterize non-ideal planar ohmic contacts in presence of inhomogeneities","authors":"L. Gutai","doi":"10.1109/ICMTS.1990.67874","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67874","url":null,"abstract":"The most widely used test procedures for electrical contact characterization are the Kelvin cross bridge resistor method, the transmission line model (TLM) test structure and their combination, which produces a six-terminal Kelvin structure. These structures measure the specific contact resistance (contact resistivity) and the semiconductor sheet resistance beneath the contact. A modified TLM structure combined with a particular evaluation method makes it possible to use the TLM method on wafers with high levels of inhomogeneities. The two independent procedures used to derive the modified method are statistical simulation and propagation of error. Statistical modeling and experimental data show that if inhomogeneities are present, electrical contact parameter extraction by conventional TLM test structures results in large errors or does not yield results at all. However, the errors in the extracted parameters can be reduced considerably using the modified TLM test method with four terminals and a data extraction method. When five terminals are used, the accuracy of the parameter extraction can also be determined by a single structure allowing separation of the die-level and wafer-level inhomogeneities.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129646198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Linewidth and step resistance distribution measurements using an addressable array 使用可寻址阵列测量线宽和阶跃电阻分布
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67885
H. Sayah, M. Buehler
{"title":"Linewidth and step resistance distribution measurements using an addressable array","authors":"H. Sayah, M. Buehler","doi":"10.1109/ICMTS.1990.67885","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67885","url":null,"abstract":"A test structure is introduced which uses column and row decoding to measure variations in linewidths and step-coverage resistances for a large sample size within a small area. A model was developed to explain the results. The structure is intended to qualify manufacturing lines used in producing ASICs. Therefore, it is designed using parameterized features to accommodate geometrical design rules. The structure was fabricated using a 2- mu m CMOS process and tested with a parametric test system. Test results show that linewidth and step resistance control is best for polysilicon layers and worst for secondary metallic layers.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115072390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信