Linewidth and step resistance distribution measurements using an addressable array

Abstract

A test structure is introduced which uses column and row decoding to measure variations in linewidths and step-coverage resistances for a large sample size within a small area. A model was developed to explain the results. The structure is intended to qualify manufacturing lines used in producing ASICs. Therefore, it is designed using parameterized features to accommodate geometrical design rules. The structure was fabricated using a 2- mu m CMOS process and tested with a parametric test system. Test results show that linewidth and step resistance control is best for polysilicon layers and worst for secondary metallic layers.<>