A. Walton, W. Gammie, D. Morrow, J. Stevenson, R. Holwill
{"title":"一种减少过程控制芯片上触点片所占面积的新方法","authors":"A. Walton, W. Gammie, D. Morrow, J. Stevenson, R. Holwill","doi":"10.1109/ICMTS.1990.67883","DOIUrl":null,"url":null,"abstract":"An approach which reduces the number of pads required by electrical test structures is presented. The multiplexed scheme requires only two levels of interconnect and enables more devices to be located in a given area, providing the designer of test structures with more freedom to experiment with structures previously requiring a large number of pads. Applications for transistors, electrical verniers, yield monitoring, reliability evaluations, continuity tests, and measuring the resistance of tracks are discussed.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"A novel approach for reducing the area occupied by contact pads on process control chips\",\"authors\":\"A. Walton, W. Gammie, D. Morrow, J. Stevenson, R. Holwill\",\"doi\":\"10.1109/ICMTS.1990.67883\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An approach which reduces the number of pads required by electrical test structures is presented. The multiplexed scheme requires only two levels of interconnect and enables more devices to be located in a given area, providing the designer of test structures with more freedom to experiment with structures previously requiring a large number of pads. Applications for transistors, electrical verniers, yield monitoring, reliability evaluations, continuity tests, and measuring the resistance of tracks are discussed.<<ETX>>\",\"PeriodicalId\":196449,\"journal\":{\"name\":\"International Conference on Microelectronic Test Structures\",\"volume\":\"65 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-03-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference on Microelectronic Test Structures\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.1990.67883\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference on Microelectronic Test Structures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.1990.67883","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel approach for reducing the area occupied by contact pads on process control chips
An approach which reduces the number of pads required by electrical test structures is presented. The multiplexed scheme requires only two levels of interconnect and enables more devices to be located in a given area, providing the designer of test structures with more freedom to experiment with structures previously requiring a large number of pads. Applications for transistors, electrical verniers, yield monitoring, reliability evaluations, continuity tests, and measuring the resistance of tracks are discussed.<>
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