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The spidermask: a new approach for yield monitoring using product adaptable test structures 蜘蛛罩:一种使用产品适应性测试结构进行产量监测的新方法
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67881
S. Beckers, C. Hiltrop
{"title":"The spidermask: a new approach for yield monitoring using product adaptable test structures","authors":"S. Beckers, C. Hiltrop","doi":"10.1109/ICMTS.1990.67881","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67881","url":null,"abstract":"An approach for yield monitoring based on a test vehicle that consists of structures, built on the underground of a high volume product is described. A specially designed metal mask, called spidermask, together with its appropriate contact mask, isolates and contacts these individual structures to create a complete yield monitor set. The major advantage of this type of structure is the close relationship between the measurement results on the test structure itself and the actual performance of the corresponding product. As a consequence, the existing yield model is adapted to conform to the yield monitor data. The spidermask was implemented in a CMOS and in a mixed bipolar-CMOS technology. The data of both yield monitors are presented, and the relationship with the yield model is demonstrated.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117004992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Full and automated determination of MOS transistor parameters in the linear region 在线性区域的MOS晶体管参数的完全和自动测定
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67891
J. Pelloie
{"title":"Full and automated determination of MOS transistor parameters in the linear region","authors":"J. Pelloie","doi":"10.1109/ICMTS.1990.67891","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67891","url":null,"abstract":"A measurement technique is presented which allows the determination of all the parameters needed to describe the linear behavior of an MOS transistor which is valid for a large range of gate voltages and drawn lengths. Analytical models can be derived from these results and introduced in simulators for mobility and access resistance. A comparison of different measurement techniques used to obtain the effective gate length is given. It is demonstrated that one simple equation is sufficient to calculate with the good precision the current in the linear region. All the techniques were implemented in a S450 Keithley parametric tester.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132905056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A technique for characterizing AC performance with a DC parametric tester 一种用直流参数测试仪表征交流性能的技术
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67908
R. Merrill, E. Issaq, E. Gomersall
{"title":"A technique for characterizing AC performance with a DC parametric tester","authors":"R. Merrill, E. Issaq, E. Gomersall","doi":"10.1109/ICMTS.1990.67908","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67908","url":null,"abstract":"A method for measuring circuit propagation delays with a DC parametric tester is demonstrated. The technique is suitable for any normal production electrical test operation. Experimental results that demonstrate exceptional accuracy (<3% error) are presented. Possible applications include improved final test yield, improved feedback to foundry on AC results, and inclusion of AC parameters in the electrical specification of the process in addition to the traditional DC parameters. The test structure consists of an on-chip CMOS ring oscillator and F/V convertor.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133372994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fault chip defect characterization for wafer scale integration 晶圆规模集成的故障芯片缺陷表征
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67882
D. Hannaman, H. Sayah, R. Allen, M. Buehler, M. Yung
{"title":"Fault chip defect characterization for wafer scale integration","authors":"D. Hannaman, H. Sayah, R. Allen, M. Buehler, M. Yung","doi":"10.1109/ICMTS.1990.67882","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67882","url":null,"abstract":"A fault chip was designed and fabricated on a 2- mu m CMOS wafer-scale integration (WSI) process with greater than 90% wafer coverage. The chip consists of pinhole array capacitors, serpentine resistors, and comb resistors. These structures are tailored to simulate the basic cell in the WSI circuit. Defect cluster analysis, using the negative binomial distribution, indicated that significant clustering occurs for a number of defect types and varies from wafer to wafer.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"271 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129051463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reducing fabrication variability in analog IC technology by the statistical error propagation method using simple test structures 利用简单测试结构的统计误差传播方法减少模拟集成电路技术的制造变异性
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67903
S. Sundaram, A. C. Carlson
{"title":"Reducing fabrication variability in analog IC technology by the statistical error propagation method using simple test structures","authors":"S. Sundaram, A. C. Carlson","doi":"10.1109/ICMTS.1990.67903","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67903","url":null,"abstract":"The statistical error propagation method is used to analyze the parametric variance of current gain and breakdown voltage in bipolar analog integrated circuits in terms of the relative variance of four process factors; emitter sheet resistance, based sheet resistance, buried layer sheet resistance, and epitaxial thickness. The dominant level of device parameter variance and the dominant process factors to which the device is sensitive are identified, using simple test structures, thereby facilitating the tightening of variability of the device parameter. This technique is useful for integrating the device data into the process control analysis and separating the effects of the critical process factors in a fabrication environment. How the process variance of analog integrated circuits is improved by this method is demonstrated.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121807927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A measurement technique for analyzing bitline mode soft errors in half-micron design DRAMs 半微米设计dram位线模式软误差分析的测量技术
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67900
N. Higaki, S. Ando, M. Taguchi
{"title":"A measurement technique for analyzing bitline mode soft errors in half-micron design DRAMs","authors":"N. Higaki, S. Ando, M. Taguchi","doi":"10.1109/ICMTS.1990.67900","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67900","url":null,"abstract":"A technique for analyzing dynamic RAM (DRAM) bitline model errors is presented. Arrayed stripe junctions are fabricated instead of bitlines and the charge collected by each stripe junction when irradiated by alpha -particles is measured. The collection mechanism is clarified and the scaling of collected charges in downscaled DRAMs is estimated, by analyzing the profile of the charge shared by each junction. In the case of folded bitline, charges collected by adjacent bitlines canceled each other because the junctions not hit by alpha -particles also collected charge by diffusion. However, when the junction width is less than 0.6 mu m, the charge collected by diffusion becomes negligible due to the potential barrier caused by channel-cut impurities. For this reason, the use of the folded bitline for cancellation of a alpha -particle induced noise will disappear in megabit DRAMs.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115564146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Enhanced SPICE MOSFET model for analog applications including parameter extraction schemes 用于模拟应用的增强SPICE MOSFET模型，包括参数提取方案
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67892
J. A. Power, W. Lane
{"title":"Enhanced SPICE MOSFET model for analog applications including parameter extraction schemes","authors":"J. A. Power, W. Lane","doi":"10.1109/ICMTS.1990.67892","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67892","url":null,"abstract":"An enhanced SPICE MOSFET circuit simulator model is presented and shown to be very effective in simulating device characteristics. During formulation of the model, special attention was given to its ability to accurately simulate device output conductance and transconductance; thus the emphasis was on ensuring the model's suitability for analog as well as digital purposes. Parameter extract procedures using both directed nonlinear least-squares strategies and direct extraction methods with straightforward analytical equation solving were developed for the model. These procedures are described, and the accuracy and suitability of the direct methods are assessed. Comparisons between the results obtained using these methods and the more general parameter optimization schemes demonstrate that the direct parameter extraction procedure can be almost as accurate as the optimization methods providing the data used are chosen carefully.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121407042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Measurement of minority carrier transport parameters in heavily doped shallow implanted layers 重掺杂浅注入层中少数载流子输运参数的测量
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67873
Y. Pan, M. Kleefstra
{"title":"Measurement of minority carrier transport parameters in heavily doped shallow implanted layers","authors":"Y. Pan, M. Kleefstra","doi":"10.1109/ICMTS.1990.67873","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67873","url":null,"abstract":"Test structures measuring the hole transport parameters in arsenic-implanted shallow emitters were designed and fabricated. The effects of annealing and gettering on the transport parameters are investigated. The measured diffusion length in implanted emitters with well-controlled processing conditions is close to the values in an epitaxially grown layer (phosphorus doped). Simplicity and reliability should allow these structures to be employed in real processing lines.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130090683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test structure for characterization of polycrystalline silicon as a diffusion source for advanced devices 表征多晶硅作为先进器件扩散源的测试结构
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67888
B. Lojek, B. Vasquez
{"title":"Test structure for characterization of polycrystalline silicon as a diffusion source for advanced devices","authors":"B. Lojek, B. Vasquez","doi":"10.1109/ICMTS.1990.67888","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67888","url":null,"abstract":"Test structures designed for measuring diffusion of impurities in both lateral and vertical directions in deposited films are described. The impact of predeposition cleans on the diffusion of impurities across film-film and film-substrate interfaces can be investigated. Although the structures are designed for studying diffusion in polycrystalline silicon, the basic idea could be applied to other films. A general description of the test structures is given, and results obtained for the lateral diffusion of arsenic in polycrystalline silicon are presented. From these results, the effective lateral diffusion coefficient for arsenic in polycrystalline silicon is determined to be 1.410 exp(-2.63/kT)(cm/sup 2//s).<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131024636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A wafer scale fail bit analysis system for VLSI memory yield improvement 一种用于提高超大规模集成电路存储器良率的晶圆级故障位分析系统
International Conference on Microelectronic Test Structures Pub Date : 1990-03-05 DOI: 10.1109/ICMTS.1990.67899
Y. Sakai, J. Sawada, W. Sakamoto, J. Murato, H. Kawamoto, K. Sakai, K. Nakamuta
{"title":"A wafer scale fail bit analysis system for VLSI memory yield improvement","authors":"Y. Sakai, J. Sawada, W. Sakamoto, J. Murato, H. Kawamoto, K. Sakai, K. Nakamuta","doi":"10.1109/ICMTS.1990.67899","DOIUrl":"https://doi.org/10.1109/ICMTS.1990.67899","url":null,"abstract":"A wafer-scale fail bit analysis system which outputs an entire wafer fail bit map (FBM) by using a data compaction technique and testing structure is developed. With this system, process defect locations on a wafer can easily be electrically recognized quickly. The processing time of wafer-scale fail bit analysis is reduced to only 2% of that required by the conventional method. An example of a wafer-scale FBM is shown.<<ETX>>","PeriodicalId":196449,"journal":{"name":"International Conference on Microelectronic Test Structures","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132721022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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