Novel test structures for the investigation of the efficiency of guard rings used for I/O-latch-up prevention

Test structures for guard ring efficiency measurements concerning input/output (I/O) latchup in integrated CMOS circuits for minority and majority carrier injection are introduced. The locations of two guard rings are varied for n/n/sup +/-epi (epitaxial) material and n-substrate. Latchup measurements were taken using a worst case detector, which simulates neighboring internal logic circuits. In non-epi material, the total efficiency of substrate guard rings for majority carrier injection, and of well guard rings for minority carrier injection is nearly equal (factor for the trigger current approximately=20). For epi material, the substrate guard rings for majority carrier injection have very little influence; but the trigger current without guard rings is already 25 times higher than for non-epi material.<>