Self-multiplexing force-sense test structures for (MOS) IC applications

Abstract

A self-multiplexing technique which enables multiple force-sense measurements to be carried out on test structures in the small area scribe lanes of product chips is presented. Instead of using separate address signals, the technique uses the distribution of stimulus and sense voltages across lines to select the proper test structure, drastically reducing the number of probe pads required. A simple, robust prototype circuit, which enables four independent test structures to be measured with only five probe pads, is presented. The technique can be extended to n(n-1) structures for n probe pads with some additional circuitry. Excellent measurement accuracy is obtained, and the circuit allows a wide range of operating conditions, remaining insensitive to process variations.<>