Yield modeling from SRAM failure analysis

Abstract

Yield models based on Poisson, bose-Einstein, and binomial statistics are compared for a 1.25 mu m CMOS process. A mixed binomial yield model is shown to most accurately describe experimental yield data for a 1.25- mu m CMOS process. The model consists of gross yield and random yield components based on gross and random defects determined on a per level basis from a static random access memory-test element group (SRAM-TEG) yield vehicle failure analysis. The random yield component consists of both binomial and negative binomial segments, hence the mixed terminology, depending on whether or not a given defect shows evidence of clustering. Simple negative binomial models become optimistic at larger chip sizes by ascribing too much importance to interlevel effects of defect clustering. Using defect size distributions measured on a per level basis, the model is shown to hold over chip variations in feature size, product type, and chip area.<>