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ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference最新文献

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A basic CAD-tool for module generation 用于模块生成的基本cad工具
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468188
L. Brange, M. Torkelson
{"title":"A basic CAD-tool for module generation","authors":"L. Brange, M. Torkelson","doi":"10.1109/ESSCIRC.1989.5468188","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468188","url":null,"abstract":"A basic CAD-tool using a simple grid-like floorplan for placement of cells of varying sizes is presented. It is focused on the generation of physical and behavioural descriptions of data paths but is also suitable for random logic, data path controllers containing PLA's, registers, counters etc. and for analog designs containing OP's, capacitors etc. Two different types of floorplans can be chosen; one resembling the standard cell design approach and one resembling the bit-slice approach. By not assembling the cells with abutment, existing general purpose cell libraries can be used. An easy modifiable interpreting lisp-like language is used as input. Three design examples are discussed, one data path for a decimation filter, one data path for a Viterbi receiver and one multiplier.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127994565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A switch level symbolic simulator 一个开关级符号模拟器
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468071
F. Vos, C. Trullemans
{"title":"A switch level symbolic simulator","authors":"F. Vos, C. Trullemans","doi":"10.1109/ESSCIRC.1989.5468071","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468071","url":null,"abstract":"The simulator presented in this paper is based on a switch level model and is used to extract the logical behaviour of MOS digital integrated circuits. Its main original features are that the simulation is achieved symbolically with all its generality.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133378219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Passive Silicon Carrier High Performance Package for VLSI VLSI无源硅载流子高性能封装
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468199
H. Schettler, V. Kreuter
{"title":"Passive Silicon Carrier High Performance Package for VLSI","authors":"H. Schettler, V. Kreuter","doi":"10.1109/ESSCIRC.1989.5468199","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468199","url":null,"abstract":"A silion-on-silicon package for 9 VLSI chips is presented. The carrier is especially designed to support the high frequency current surges of complementary logic like CMOS or BICMOS. It contains integrated decoupling capacitors and uses 3 layers of metal. The chips are mounted via `controlled collapse chip connection'. A /370 processor containing 9 CMOS chips has been assembled. Functionality and manufacturability have successfully been demonstrated.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133803522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Parallel Decomposition in Logic Synthesis 逻辑综合中的并行分解
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468151
Krzysztof Jasinski, Tadeusz kuba, J. Kalinowski
{"title":"Parallel Decomposition in Logic Synthesis","authors":"Krzysztof Jasinski, Tadeusz kuba, J. Kalinowski","doi":"10.1109/ESSCIRC.1989.5468151","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468151","url":null,"abstract":"In this paper a new approach to logic synthesis in VLSI design, based on parallel decomposition, is proposed. The idea is to use an effective method for multiple-output function reduction to select a decomposition that yields minimal silicon area in the final implementation. Experimental results and assessment of this synthesis method are provided.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122794527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An S and C Band GaAs Single Chip Combined Phase Shifter and Amplifier 一种S和C波段砷化镓移相器和放大器组合芯片
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468047
A. Lane, F. Myers, S. Amos, D. Parker
{"title":"An S and C Band GaAs Single Chip Combined Phase Shifter and Amplifier","authors":"A. Lane, F. Myers, S. Amos, D. Parker","doi":"10.1109/ESSCIRC.1989.5468047","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468047","url":null,"abstract":"This paper describes the design and measured results of a multifunction MMIC designed for phased array applications. The circuit has a six bit switched filter phase shifter, five amplifiers and two SPDT transmit receive routing switches. The band of operation is 2 - 6GHz and the chip size is 5.8mm × 1.8mm (area ¿ 10.5 mm2). The maximum measured gain is 22dB and the worst case measured input return loss is 14dB. It is believed that the multifunction MMIC to be described is one of the worlds most complex working analogue GaAs MMIC's.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116564317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automatic Synthesis of Multilevel Combinational Logic 多层组合逻辑的自动合成
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468158
A. C. Andersen, J. Madsen, H. Pallisgaard, DK-2800 Lyngby, Denmark
{"title":"Automatic Synthesis of Multilevel Combinational Logic","authors":"A. C. Andersen, J. Madsen, H. Pallisgaard, DK-2800 Lyngby, Denmark","doi":"10.1109/ESSCIRC.1989.5468158","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468158","url":null,"abstract":"This paper describes a system for the synthesis of multilevel combinational logic, transforming functional description into mask layout. The system includes a logic synthesis part, partly consisting of tools developed at Eindhoven University of Technology, which has been interfaced to the layout synthesis part in the CATOE-system, developed at the DesignCenter of Electronics Institute. The various steps in the transformation are presented together with a complete design example, implementing a multi-output combinational decoder function.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123625167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimization of an Oversampling Feedback Coder for Signal Processing Chips 信号处理芯片过采样反馈编码器的优化
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468169
F. Dielacher
{"title":"Optimization of an Oversampling Feedback Coder for Signal Processing Chips","authors":"F. Dielacher","doi":"10.1109/ESSCIRC.1989.5468169","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468169","url":null,"abstract":"This paper describes the design of a special type of oversampling coder, a so called adaptive interpolative delta modulator. This type of coder incorporates most of the known tricks for improving the signal to noise ratio of an oversampling feedback coder. This system provides higher quality of the processable code than other coders. Due to that fact, the oversampling ratio is substantially reduced. The loop parameters are optimized by means of a software model, which results from a very accurate analytical model. The coder is used in a codec filter chip with digitaly programmable gain. In order to achieve a sufficient programmable gain range in the digital part, the coder and decoder must have a dynamic range of more than 90 dB which has to be achieved in the presence of large amounts of digital switching. Including the loop delay in the analytical model and modelling the circuit nonidealities correctly leads to a coder with a dynamic range of almost 94 dB. Results presented are based on both simulations and measurements.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123793728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
AH-JFET Amplifiers For Low Noise Applications 用于低噪声应用的AH-JFET放大器
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468140
W. Buttler, B. Hosticka
{"title":"AH-JFET Amplifiers For Low Noise Applications","authors":"W. Buttler, B. Hosticka","doi":"10.1109/ESSCIRC.1989.5468140","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468140","url":null,"abstract":"In this contribution we present amplifiersfor low noise applications. They have been designed using only N- and P-channel CMOS-compatible junction field effect transistors (JFET) for biasing, amplification, and switching. Using these components a very low noise amplifier system was integrated which consists of a charge sensitive preamplifier and an SC noise filter. Since all active components in this circuit are made of CMOS-compatible JFET's, the amplifier system is also radiation hardened.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125257633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design Methods for Complex Digital Circuits 复杂数字电路的设计方法
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468152
W. Nebel
{"title":"Design Methods for Complex Digital Circuits","authors":"W. Nebel","doi":"10.1109/ESSCIRC.1989.5468152","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468152","url":null,"abstract":"The paper classifies different types of digital IC products emerging from enhanced technology. The different production volumes to be expected for the different classes are analyzed with respect to key cost drivers. A new class of high complex application specific products with moderate production volume but increasing market share is identified. General strategies for managing and reducing complexity are analyzed with respect to their applicability to IC design. The ASC hierarchical design methodology based on abstraction and high level modeling is presented. The integrated ASC Chip Design System is outlined.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126896670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Single Chip 5 Volt 2400 Bps Modem 单片5伏2400 Bps调制解调器
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468101
Stephen D. Levy, P. Hurst, P. Ju, J. Huggins, C. R. Cole
{"title":"A Single Chip 5 Volt 2400 Bps Modem","authors":"Stephen D. Levy, P. Hurst, P. Ju, J. Huggins, C. R. Cole","doi":"10.1109/ESSCIRC.1989.5468101","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468101","url":null,"abstract":"A single-chip 2400 bps modem which has been implemented in a 3.6 ¿m Si gate CMOS process will be described. An analog front end (AFE) and digital signal processor (DSP) are included on the IC. The transmit-side and part of the receive-side signal processing are performed in the analog domain. The DSP is dedicated to receive signal processing - timing recovery, adaptive equalization, carrier recovery/demodulation and decoding. The chip operates off a single 5 V supply, occupies 68.8 mm2 and dissipates 120 mW. The design and performance of the IC will be presented.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"230 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127011495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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