{"title":"A basic CAD-tool for module generation","authors":"L. Brange, M. Torkelson","doi":"10.1109/ESSCIRC.1989.5468188","DOIUrl":null,"url":null,"abstract":"A basic CAD-tool using a simple grid-like floorplan for placement of cells of varying sizes is presented. It is focused on the generation of physical and behavioural descriptions of data paths but is also suitable for random logic, data path controllers containing PLA's, registers, counters etc. and for analog designs containing OP's, capacitors etc. Two different types of floorplans can be chosen; one resembling the standard cell design approach and one resembling the bit-slice approach. By not assembling the cells with abutment, existing general purpose cell libraries can be used. An easy modifiable interpreting lisp-like language is used as input. Three design examples are discussed, one data path for a decimation filter, one data path for a Viterbi receiver and one multiplier.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1989.5468188","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
A basic CAD-tool using a simple grid-like floorplan for placement of cells of varying sizes is presented. It is focused on the generation of physical and behavioural descriptions of data paths but is also suitable for random logic, data path controllers containing PLA's, registers, counters etc. and for analog designs containing OP's, capacitors etc. Two different types of floorplans can be chosen; one resembling the standard cell design approach and one resembling the bit-slice approach. By not assembling the cells with abutment, existing general purpose cell libraries can be used. An easy modifiable interpreting lisp-like language is used as input. Three design examples are discussed, one data path for a decimation filter, one data path for a Viterbi receiver and one multiplier.