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ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference最新文献

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A 23ns 1Mbit BiCMOS DRAM 一个23ns 1Mbit的BiCMOS DRAM
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468110
K. Yanagisawa, Goro Kitsukawa, Yutaka Kobayashi, Y. Kinoshita, Tatsuyuki Ohta, Tetsu Udagawa, Kyoko Ishii, Hitoshi Miwa, Hiroyuki Miyazawa, Yoshiaki Ouchi, Hiromi Tsukada, Tetsuro Matsumoto, Kiyoo Itoh
{"title":"A 23ns 1Mbit BiCMOS DRAM","authors":"K. Yanagisawa, Goro Kitsukawa, Yutaka Kobayashi, Y. Kinoshita, Tatsuyuki Ohta, Tetsu Udagawa, Kyoko Ishii, Hitoshi Miwa, Hiroyuki Miyazawa, Yoshiaki Ouchi, Hiromi Tsukada, Tetsuro Matsumoto, Kiyoo Itoh","doi":"10.1109/ESSCIRC.1989.5468110","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468110","url":null,"abstract":"I -_JLd Lioduction Bit density oi DRAMs has continued to be improved by a factor of four times every three years. In contrast with these remarkable improvemenls in bit densitv, improvements in access and cycle times of DRAMs available in the market are insufficient for higher performance applications. For improving DRAM speed with reasonable process complexity, a 1.3ßm 1Mbit BiCMOS DRAM has been reported (I). However, performance of the previous DRAM is insufficient, although BiCMOS technology was verified as having advantages for improving speed, power dissipation and soft error rate (2)(3). In this paper, a 23ns 1.3 fi m 1Mbit BiCMOS DRAM, suitable for imss production, is described. First, high-speed sensing circuit techniques combined with a non","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115136581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Analysis and Improvements of Highly Accurate Dynamic Current Mirrors 高精度动态电流镜的分析与改进
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468052
G. Wegmann, E. Vittoz
{"title":"Analysis and Improvements of Highly Accurate Dynamic Current Mirrors","authors":"G. Wegmann, E. Vittoz","doi":"10.1109/ESSCIRC.1989.5468052","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468052","url":null,"abstract":"Possibilities and improvements are considered of realizing highly accurate dynamic current mirrors based on dynamic analog techniques. These current mirrors, which individually memorize the input current, are insensitive to the transistor mismatch. The interferring parameters are presented, improvements proposed and experimental results shown.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125826991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Programmable 2D linear filter for video applications 用于视频应用的可编程2D线性滤波器
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/4.102668
R. Hofer, W. Kamp, R. Kunemund, H. Soldner
{"title":"Programmable 2D linear filter for video applications","authors":"R. Hofer, W. Kamp, R. Kunemund, H. Soldner","doi":"10.1109/4.102668","DOIUrl":"https://doi.org/10.1109/4.102668","url":null,"abstract":"In this paper a fully integrated two dimensional linear filter including a line buffer for a 7×7 kernel is presented. To run the filter in real time at video clock frequencies an array of pipelined carry-save adders was used as a very fast arithmetic unit.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122298380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Integrated Selectivity for Narrow-Band FM IF Systems 窄带调频中频系统的综合选择性
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/4.102671
F. Krummenacher, G. van Ruymbeke
{"title":"Integrated Selectivity for Narrow-Band FM IF Systems","authors":"F. Krummenacher, G. van Ruymbeke","doi":"10.1109/4.102671","DOIUrl":"https://doi.org/10.1109/4.102671","url":null,"abstract":"An 18th-order all-pole continuous-time bandpass filter for IF filtering purposes has been designed and integrated in a 3 ¿m CMOS process. Implemented using nine fully-balanced, transconductor-capacitor coupled resonators, the filter features 20 kHz bandwidth at 200 kHz center frequency, 54 dB dynamic range (IM3 ≪ - 40 dB) and consumes 300 ¿A from a single 4 V supply.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122551832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
SLOCOP-II: Improved accuracy and efficiency in Timing Verification, based on logic functionality and MOS circuit hierarchy sloop - ii:基于逻辑功能和MOS电路层次结构，提高时序验证的准确性和效率
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468072
P. Johannes, P. Das, L. Claesen, H. de Man
{"title":"SLOCOP-II: Improved accuracy and efficiency in Timing Verification, based on logic functionality and MOS circuit hierarchy","authors":"P. Johannes, P. Das, L. Claesen, H. de Man","doi":"10.1109/ESSCIRC.1989.5468072","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468072","url":null,"abstract":"The new SLOCOP-II timing verifier for MOSVLSI circuits is presented. Existing timing verifiers do not take into account the logic functionality and can give rise to serious overestimates for the circuit delays. In SLOCOP-II new false path avoidance algorithms have been implemented taking into account the logic functionality of the circuits. For the purpose of generality new methods for event determination have been developed and are presented in this paper. The circuit hierarchy is exploited in order to allow for faster evaluations. Timing verification results are given for instances of the parameterised modules in the CATHEDRAL-II library.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124140867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A High Speed Analog Data Multichannel Acquisition System 高速模拟数据多通道采集系统
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468170
J. Moschen, A. Caldwell, L. Hervás, B. Hosticka, U. Kotz, B. Sippach
{"title":"A High Speed Analog Data Multichannel Acquisition System","authors":"J. Moschen, A. Caldwell, L. Hervás, B. Hosticka, U. Kotz, B. Sippach","doi":"10.1109/ESSCIRC.1989.5468170","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468170","url":null,"abstract":"We present an analog data multichannel acquisition system based on two different VLSI CMOS chips, which is used for high speed event acquisition tasks. Although using only one low speed ADC the system offers the capability to process events of twelve analog channels with a maximum sampling frequency of 18 MHz. The cascadable custom chips include analog pipelines with a storage depth of 58 samples, analog buffer memories for events containing up to eight samples and an analog multiplexer for twelve event channels and additional thirteen DC channels. In the paper the chips and system architecture will be discussed and measurements from integrated prototypes will be given.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132216976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 700 Volts Interface IC for Power Bridge Circuits 用于功率桥电路的700伏接口集成电路
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/4.102660
F. Schoofs, C. Dupont
{"title":"A 700 Volts Interface IC for Power Bridge Circuits","authors":"F. Schoofs, C. Dupont","doi":"10.1109/4.102660","DOIUrl":"https://doi.org/10.1109/4.102660","url":null,"abstract":"In this paper a 700 Volts integrated interface circuit is described, which provides the gate drive for the high-side and the ground-side power MOS transistor in an off-line half-bridge circuit. Ground separation for good inter-system EMC and a number of new provisions to alleviate control requirements towards the low power system control part are included.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130970853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
The Design of Scaled-Down Submicron 1Mb ECL/TTL BiCMOS SRAMs 缩小亚微米1Mb ECL/TTL BiCMOS ram的设计
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468109
Y. Urakawa, Katsuhiko Sato, M. Matsui
{"title":"The Design of Scaled-Down Submicron 1Mb ECL/TTL BiCMOS SRAMs","authors":"Y. Urakawa, Katsuhiko Sato, M. Matsui","doi":"10.1109/ESSCIRC.1989.5468109","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468109","url":null,"abstract":"INTRODUCTION BiCMOS scalability problem is considered to be serious in submicron generation devices because BiCMOS combination logic gates lose their speed advantage to CMOS logic gates as an external supply voltage is scaled-down to 3.3V [1], Actually for CMOS logic gates, external 3.3V supply voltage has various merits in the light of hot-carrier induced MOSFET degradation, time-dependent dielectric breakdown (TDDB) of gate oxide, power-reduction and so on. However, it is disadvantageous that 3.3V supply voltage devices are not compatible to former generation devices of 5V power supply. This paper will describe 5V-only BiCMOS SRAM architecture covering from 0.8jim to 0.5|im design rules and its application to lM-bit ECL/TTL SRAMs [2,3]. Two-way BiCMOS internal voltage supply, together with newly developed interface circuits, prevents MOSFET gate-drain voltage exceeding breakdown voltage to assure MOSFET reliability, and can optimize the oxide thickness so as to minimize the gate delay.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114774868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a low-noise 100-MHz balanced Schmitt-trigger oscillator 低噪声100mhz平衡施密特触发振荡器的设计
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468046
J. Sneep, C. Verhoeven
{"title":"Design of a low-noise 100-MHz balanced Schmitt-trigger oscillator","authors":"J. Sneep, C. Verhoeven","doi":"10.1109/ESSCIRC.1989.5468046","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468046","url":null,"abstract":"In this paper we present the realization of a new low-noise, balanced Schmitt-trigger oscillator in a high frequency bipolar process. Because of the absence of a floating capacitor and its differential architecture it is especially suited for high-frequency oscillators. It does also have low phase noise, which is close to the theoretical value.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127941321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 16Mbit DRAM Test Device 一个16Mbit的DRAM测试设备
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468122
W. Raab, M. Beurer, H. Eichfeld, H. Geib, D. Gleis, T. Kunemund, K. Lau, B. Lustig, H. Mattes, M. Peisl, R. Tielert
{"title":"A 16Mbit DRAM Test Device","authors":"W. Raab, M. Beurer, H. Eichfeld, H. Geib, D. Gleis, T. Kunemund, K. Lau, B. Lustig, H. Mattes, M. Peisl, R. Tielert","doi":"10.1109/ESSCIRC.1989.5468122","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468122","url":null,"abstract":"A test device used for the development of a 16Mbit DRAM is described. It allows to compare different architectural options on one chip, such as different numbers of cells per bitline, or different ways to use second aluminum in pitch circuits and periphery efficiently. On-chip voltage reduction circuits are explained and simulation waveforms are shown. An accurate simulation model for the operating conditions of the sense amplifiers has been developed. Optimization of the driver circuit as well as reduction of the driveline resistance are necessary. The second stage sensing is discussed in conjunction with a new wordline test mode, which permits the test of up to all bits along a wordline in parallel. With this innovation wordline test modes in product DRAMs are no longer a privilege for designs with global bitlines.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126275280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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