A 23ns 1Mbit BiCMOS DRAM

ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI:10.1109/ESSCIRC.1989.5468110

K. Yanagisawa, Goro Kitsukawa, Yutaka Kobayashi, Y. Kinoshita, Tatsuyuki Ohta, Tetsu Udagawa, Kyoko Ishii, Hitoshi Miwa, Hiroyuki Miyazawa, Yoshiaki Ouchi, Hiromi Tsukada, Tetsuro Matsumoto, Kiyoo Itoh

引用次数: 4

Abstract

I -_JLd Lioduction Bit density oi DRAMs has continued to be improved by a factor of four times every three years. In contrast with these remarkable improvemenls in bit densitv, improvements in access and cycle times of DRAMs available in the market are insufficient for higher performance applications. For improving DRAM speed with reasonable process complexity, a 1.3ßm 1Mbit BiCMOS DRAM has been reported (I). However, performance of the previous DRAM is insufficient, although BiCMOS technology was verified as having advantages for improving speed, power dissipation and soft error rate (2)(3). In this paper, a 23ns 1.3 fi m 1Mbit BiCMOS DRAM, suitable for imss production, is described. First, high-speed sensing circuit techniques combined with a non

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一个23ns 1Mbit的BiCMOS DRAM

dram的钻头密度每三年提高四倍。与比特密度的这些显著改进相比，市场上可用的dram在访问和周期时间方面的改进不足以满足更高性能的应用。为了在合理的工艺复杂度下提高DRAM的速度，已经报道了1.3ßm 1Mbit BiCMOS DRAM (I)。然而，尽管BiCMOS技术在提高速度、功耗和软错误率方面具有优势，但之前的DRAM性能不足(2)(3)。本文介绍了一种适用于imss生产的23ns 1.3 fim 1Mbit BiCMOS DRAM。首先，将高速传感电路技术与非相结合

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference

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