SLOCOP-II: Improved accuracy and efficiency in Timing Verification, based on logic functionality and MOS circuit hierarchy

Abstract

The new SLOCOP-II timing verifier for MOSVLSI circuits is presented. Existing timing verifiers do not take into account the logic functionality and can give rise to serious overestimates for the circuit delays. In SLOCOP-II new false path avoidance algorithms have been implemented taking into account the logic functionality of the circuits. For the purpose of generality new methods for event determination have been developed and are presented in this paper. The circuit hierarchy is exploited in order to allow for faster evaluations. Timing verification results are given for instances of the parameterised modules in the CATHEDRAL-II library.