A 16Mbit DRAM Test Device

Abstract

A test device used for the development of a 16Mbit DRAM is described. It allows to compare different architectural options on one chip, such as different numbers of cells per bitline, or different ways to use second aluminum in pitch circuits and periphery efficiently. On-chip voltage reduction circuits are explained and simulation waveforms are shown. An accurate simulation model for the operating conditions of the sense amplifiers has been developed. Optimization of the driver circuit as well as reduction of the driveline resistance are necessary. The second stage sensing is discussed in conjunction with a new wordline test mode, which permits the test of up to all bits along a wordline in parallel. With this innovation wordline test modes in product DRAMs are no longer a privilege for designs with global bitlines.