{"title":"RIM: Routing Into Macrocells and application to an arithmetic processor","authors":"A. Guyot","doi":"10.1109/ESSCIRC.1989.5468181","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468181","url":null,"abstract":"This paper presents first a silicon assembler and then a router. The two programs have to be described together since the router uses tracks, terminals and obstacles that are build by the assembler. Using tracks that run inside the macrocells dramatically reduces the area demanded for routing. An example of assembling and routing of a mathematicalfunctions processor [1,2,3] is provided at the end of the paper.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122847663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"BiCMOS for High Performance Analog and Digital Circuits","authors":"H. Pfleiderer, A. Wieder, K. Hart","doi":"10.1109/ESSCIRC.1989.5468121","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468121","url":null,"abstract":"As a result of its high packing density, low power dissipation and ease of design, CMOS has in recent years emerged as the standard technology for VLSI circuits. Compared to CMOS, bipolar technology offers better analog features, e.g. offset voltage as well as unique speed advantages. ECL processors, for example, operate at clock rates over 100MHz whereas CMOS processors operate typically at 30MHz. Thus bipolar and CMOS devices form an ideal combination. The only drawback is the higher cost of their fabrication on the same chip. BiCMOS processes are more costly than CMOS processes due to additional masks, processing steps and reduced yield. However, this cost factor is less severe today than in earlier years because of the convergence of bipolar and CMOS technologies. This report describes BiCMOS techniques for high-speed/ high-density circuits for digital as well as analog functions. First the features of MOS and bipolar devices are compared. The different aspects of designing a BiCMOS process are described next. Finally the advantages of the BiCMOS technology for systems applications are demonstrated.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122071175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Worst Case Design and Datasheet Generation Techniques for Analog Silicon Compilers","authors":"B. Goffart, J. Jongsma, M. Degrauwe","doi":"10.1109/ESSCIRC.1989.5468146","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468146","url":null,"abstract":"Worst case design and datasheet generation techniques for analog circuits, based on analytic expressions, are presented. They take into account temperature, bias current and technology parameter fluctuations. The techniques which have been implemented in an analog design system, operating with \"design strategies\" as well as \"numerical optimization methods\", do not degrade significantly the design time.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122840695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Sigma-Delta versus Binary Weighted AD/DA conversion, what is the most promising?","authors":"E. Dijkmans, P. Naus","doi":"10.1109/ESSCIRC.1989.5468193","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468193","url":null,"abstract":"Though conversion of analog signals to and from digital data is supposed to be a mature, well defined technology, the application in digital signal processing like digital audio unveiled a number of neglected artifacts. Also the correlation between audibility and type of imperfection in the converted signal is only partly covered. Test signals as used on CD records explore only a small part of the converter characteristic with sufficient detail. Bias-dependent glitches, slew-rate distortion, noise-switching, clock-jitter and parasitic coupling, which can seriously degrade the signal, are mostly ignored. The reproduction of low-level signals requires differential linearity to be much better than usually specified. Low-level distortion is produced at every place in the chain between analog input signal and analog output signal where quantization or conversion errors are introduced. In general this distortion is reduced by adding noise as a dither signal to de-correlate errors. The amplitude of the dither varies from one LSB step to several LSB steps, depending on the error to be de-correlated, at the expense of a considerable loss in dynamic range. Error feed-back by noise-shaping can be used to reduce quantization distortion if over-sampling is sufficiently high. Dithering or noise-shaping however can emphasize certain non-linearities generated by the D/A converter, e.g. like level-dependent glitches. Converters that guarantee good low-level reproduction are oversampled noise-shaping coders. These coders obtain linearity by time-averaging in stead of by analog precision.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124069812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Sparsø, H. N. Jorgensen, E. Paaske, Steen Pedersen, T. Rubner-Petersen
{"title":"A Fully Parallel VLSI-implementation of the Viterbi Decoding Algorithm","authors":"J. Sparsø, H. N. Jorgensen, E. Paaske, Steen Pedersen, T. Rubner-Petersen","doi":"10.1109/ESSCIRC.1989.5468082","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468082","url":null,"abstract":"In this paper we describe the implementation of a K = 7, R = 1/2 single-chip Viterbi decoder intended to operate at 10-20 Mbit/sec. We propose a general, regular and area efficient floor-plan that is also suitable for implementation of decoders for codes with different generator polynomials or different values of K. The Shuffle-Exchange type interconnection network is implemented by organizing the 64 processing elements to form a ring. The ring is laid out in two columns, and the interconnections between non-neighbours are routed in the channel between the columns. The interconnection network occupies 32 % of the area, and the global signals (including power) occupy a further 10 %. A test-chip containing a pair of processing elements has been fabricated via NORCHIP (the Scandinavian CMOS IC prototype implementation service). This chip has been fully tested, and it operates correctly at speeds above 26 MHz under worst-case conditions (VDD = 4.75 V and TA = 70 °C).","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125997976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 110MHz CMOS Transconductance-C Low-Pass Filter","authors":"B. Nauta, E. Seevinck","doi":"10.1109/ESSCIRC.1989.5468134","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468134","url":null,"abstract":"A CMOS third order elliptic low-pass filter with a 110MHz cut-off frequency realized in a 3¿m-process is presented. The filter consists of differential transconductance elements and capacitors. The transconductance element has good linearity properties and an excellent high frequency behaviour thanks to the absence ofinternal nodes. Both the cut-off frequency and the Q-factors can be tuned.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124902267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimization of Submicron CMOS Differential Pass-Transistor Logic","authors":"J. Pasternak, C. Salama","doi":"10.1109/ESSCIRC.1989.5468086","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468086","url":null,"abstract":"Techniques for significantly enhancing the speed of CMOS differential pass-transistor logic (DPTL) are presented. Use is made of the noise immunity features of DPTL to enable signal swing reductions that result in increased speed. A novel single-phase clocking scheme using a new DPTL buffer is proposed. Experimental results are provided for a DPTL divide-by-N prescaler (1 ¿ N ¿ 64) implemented in a 0.8¿m CMOS technology.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124299944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 60 × 58 Integrated Multiplier","authors":"K. Helwig, K. Getzlaff, S. D. Trong","doi":"10.1109/ESSCIRC.1989.5468056","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468056","url":null,"abstract":"A dense 60 × 58 Multiplier will be described which is integrated on a chip containing a complete Coprocessor. The Multiplier has been fabricated in a triple-metal, single-polysilicon CMOS process with 1.0 um lithography and CMOS devices with 0.5 um effective channel length. Circuit techniques are described that obtain a multiplier with high density (3.5mm × 5.7mm) and high speed. The typical delay is 18 ns.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121899850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Schmitt-Landsiedel, B. Hoppe, G. Neuendorf, M. Wurm, J. Winnerl
{"title":"Pipelined 16k Buffer RAM with 300MHz Operating Frequency","authors":"D. Schmitt-Landsiedel, B. Hoppe, G. Neuendorf, M. Wurm, J. Winnerl","doi":"10.1109/ESSCIRC.1989.5468115","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468115","url":null,"abstract":"A new pipeline architecture for fast CMOS buffer SRAMs is presented that allows operation at very high clock rates. The high speed is achieved by use of a hierarchical architecture and a memory cell with separate read and write data lines.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123124202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Time-Jitter and Instabilities of Gbit/S IC'S Caused by Transmission-Line Interconnections","authors":"J. Hauenschild, H. Rein","doi":"10.1109/ESSCIRC.1989.5468081","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468081","url":null,"abstract":"The influence of transmission-line interconnections between high-speed IC's on time jitter and oscillations is investigated. Simple but flexible methods for estimating these effects are proposed and proved by measurements. The estimations are based on small-signal S-parameter simulations (or measurements). Moreover, various line terminations are discussed. A special Gbit/s bipolar IC was fabricated for the experiments.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"629 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133101930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}