{"title":"一个60 × 58集成乘法器","authors":"K. Helwig, K. Getzlaff, S. D. Trong","doi":"10.1109/ESSCIRC.1989.5468056","DOIUrl":null,"url":null,"abstract":"A dense 60 × 58 Multiplier will be described which is integrated on a chip containing a complete Coprocessor. The Multiplier has been fabricated in a triple-metal, single-polysilicon CMOS process with 1.0 um lithography and CMOS devices with 0.5 um effective channel length. Circuit techniques are described that obtain a multiplier with high density (3.5mm × 5.7mm) and high speed. The typical delay is 18 ns.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 60 × 58 Integrated Multiplier\",\"authors\":\"K. Helwig, K. Getzlaff, S. D. Trong\",\"doi\":\"10.1109/ESSCIRC.1989.5468056\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A dense 60 × 58 Multiplier will be described which is integrated on a chip containing a complete Coprocessor. The Multiplier has been fabricated in a triple-metal, single-polysilicon CMOS process with 1.0 um lithography and CMOS devices with 0.5 um effective channel length. Circuit techniques are described that obtain a multiplier with high density (3.5mm × 5.7mm) and high speed. The typical delay is 18 ns.\",\"PeriodicalId\":187183,\"journal\":{\"name\":\"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1989.5468056\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1989.5468056","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A dense 60 × 58 Multiplier will be described which is integrated on a chip containing a complete Coprocessor. The Multiplier has been fabricated in a triple-metal, single-polysilicon CMOS process with 1.0 um lithography and CMOS devices with 0.5 um effective channel length. Circuit techniques are described that obtain a multiplier with high density (3.5mm × 5.7mm) and high speed. The typical delay is 18 ns.
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