ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference最新文献

筛选
英文 中文
Sigma-Delta versus Binary Weighted AD/DA conversion, what is the most promising? Sigma-Delta和二元加权AD/DA转换,哪个最有前途?
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468193
E. Dijkmans, P. Naus
{"title":"Sigma-Delta versus Binary Weighted AD/DA conversion, what is the most promising?","authors":"E. Dijkmans, P. Naus","doi":"10.1109/ESSCIRC.1989.5468193","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468193","url":null,"abstract":"Though conversion of analog signals to and from digital data is supposed to be a mature, well defined technology, the application in digital signal processing like digital audio unveiled a number of neglected artifacts. Also the correlation between audibility and type of imperfection in the converted signal is only partly covered. Test signals as used on CD records explore only a small part of the converter characteristic with sufficient detail. Bias-dependent glitches, slew-rate distortion, noise-switching, clock-jitter and parasitic coupling, which can seriously degrade the signal, are mostly ignored. The reproduction of low-level signals requires differential linearity to be much better than usually specified. Low-level distortion is produced at every place in the chain between analog input signal and analog output signal where quantization or conversion errors are introduced. In general this distortion is reduced by adding noise as a dither signal to de-correlate errors. The amplitude of the dither varies from one LSB step to several LSB steps, depending on the error to be de-correlated, at the expense of a considerable loss in dynamic range. Error feed-back by noise-shaping can be used to reduce quantization distortion if over-sampling is sufficiently high. Dithering or noise-shaping however can emphasize certain non-linearities generated by the D/A converter, e.g. like level-dependent glitches. Converters that guarantee good low-level reproduction are oversampled noise-shaping coders. These coders obtain linearity by time-averaging in stead of by analog precision.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124069812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A Fully Parallel VLSI-implementation of the Viterbi Decoding Algorithm Viterbi译码算法的全并行vlsi实现
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468082
J. Sparsø, H. N. Jorgensen, E. Paaske, Steen Pedersen, T. Rubner-Petersen
{"title":"A Fully Parallel VLSI-implementation of the Viterbi Decoding Algorithm","authors":"J. Sparsø, H. N. Jorgensen, E. Paaske, Steen Pedersen, T. Rubner-Petersen","doi":"10.1109/ESSCIRC.1989.5468082","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468082","url":null,"abstract":"In this paper we describe the implementation of a K = 7, R = 1/2 single-chip Viterbi decoder intended to operate at 10-20 Mbit/sec. We propose a general, regular and area efficient floor-plan that is also suitable for implementation of decoders for codes with different generator polynomials or different values of K. The Shuffle-Exchange type interconnection network is implemented by organizing the 64 processing elements to form a ring. The ring is laid out in two columns, and the interconnections between non-neighbours are routed in the channel between the columns. The interconnection network occupies 32 % of the area, and the global signals (including power) occupy a further 10 %. A test-chip containing a pair of processing elements has been fabricated via NORCHIP (the Scandinavian CMOS IC prototype implementation service). This chip has been fully tested, and it operates correctly at speeds above 26 MHz under worst-case conditions (VDD = 4.75 V and TA = 70 °C).","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125997976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 110MHz CMOS Transconductance-C Low-Pass Filter 110MHz CMOS跨导c低通滤波器
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468134
B. Nauta, E. Seevinck
{"title":"A 110MHz CMOS Transconductance-C Low-Pass Filter","authors":"B. Nauta, E. Seevinck","doi":"10.1109/ESSCIRC.1989.5468134","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468134","url":null,"abstract":"A CMOS third order elliptic low-pass filter with a 110MHz cut-off frequency realized in a 3¿m-process is presented. The filter consists of differential transconductance elements and capacitors. The transconductance element has good linearity properties and an excellent high frequency behaviour thanks to the absence ofinternal nodes. Both the cut-off frequency and the Q-factors can be tuned.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124902267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Optimization of Submicron CMOS Differential Pass-Transistor Logic 亚微米CMOS差分通管逻辑的优化
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468086
J. Pasternak, C. Salama
{"title":"Optimization of Submicron CMOS Differential Pass-Transistor Logic","authors":"J. Pasternak, C. Salama","doi":"10.1109/ESSCIRC.1989.5468086","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468086","url":null,"abstract":"Techniques for significantly enhancing the speed of CMOS differential pass-transistor logic (DPTL) are presented. Use is made of the noise immunity features of DPTL to enable signal swing reductions that result in increased speed. A novel single-phase clocking scheme using a new DPTL buffer is proposed. Experimental results are provided for a DPTL divide-by-N prescaler (1 ¿ N ¿ 64) implemented in a 0.8¿m CMOS technology.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124299944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 60 × 58 Integrated Multiplier 一个60 × 58集成乘法器
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468056
K. Helwig, K. Getzlaff, S. D. Trong
{"title":"A 60 × 58 Integrated Multiplier","authors":"K. Helwig, K. Getzlaff, S. D. Trong","doi":"10.1109/ESSCIRC.1989.5468056","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468056","url":null,"abstract":"A dense 60 × 58 Multiplier will be described which is integrated on a chip containing a complete Coprocessor. The Multiplier has been fabricated in a triple-metal, single-polysilicon CMOS process with 1.0 um lithography and CMOS devices with 0.5 um effective channel length. Circuit techniques are described that obtain a multiplier with high density (3.5mm × 5.7mm) and high speed. The typical delay is 18 ns.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121899850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pipelined 16k Buffer RAM with 300MHz Operating Frequency 流水线16k缓冲RAM与300MHz的工作频率
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468115
D. Schmitt-Landsiedel, B. Hoppe, G. Neuendorf, M. Wurm, J. Winnerl
{"title":"Pipelined 16k Buffer RAM with 300MHz Operating Frequency","authors":"D. Schmitt-Landsiedel, B. Hoppe, G. Neuendorf, M. Wurm, J. Winnerl","doi":"10.1109/ESSCIRC.1989.5468115","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468115","url":null,"abstract":"A new pipeline architecture for fast CMOS buffer SRAMs is presented that allows operation at very high clock rates. The high speed is achieved by use of a hierarchical architecture and a memory cell with separate read and write data lines.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123124202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Time-Jitter and Instabilities of Gbit/S IC'S Caused by Transmission-Line Interconnections 传输在线互连引起的Gbit/S集成电路的时间抖动和不稳定性
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468081
J. Hauenschild, H. Rein
{"title":"Time-Jitter and Instabilities of Gbit/S IC'S Caused by Transmission-Line Interconnections","authors":"J. Hauenschild, H. Rein","doi":"10.1109/ESSCIRC.1989.5468081","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468081","url":null,"abstract":"The influence of transmission-line interconnections between high-speed IC's on time jitter and oscillations is investigated. Simple but flexible methods for estimating these effects are proposed and proved by measurements. The estimations are based on small-signal S-parameter simulations (or measurements). Moreover, various line terminations are discussed. A special Gbit/s bipolar IC was fabricated for the experiments.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"629 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133101930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 500 MHz Output Direct Frequency Synthesiser 500兆赫输出直接频率合成器
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468067
P. Saul, D. G. Taylor, T. Ward
{"title":"A 500 MHz Output Direct Frequency Synthesiser","authors":"P. Saul, D. G. Taylor, T. Ward","doi":"10.1109/ESSCIRC.1989.5468067","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468067","url":null,"abstract":"First results are now available on a UHF synthesiser, which is primarily intended for radar and electronic warfare applications. The device generates square and triangle wave outputs, true and complement, phase and quadrature, over the range 1Hz to 500MHz. It is a fully integrated design, including two Digital to Analogue Converters (DACs) which each have a faster operating specification than any DAC currently available. The circuit is composed of a number of structured circuit blocks, each of which can be tested independently on the chip. This approach has benefits both during device evaluation and as an aid to minimising production test times.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"16 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114024921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analog Circuit Design Optimization based on Symbolic Simulation and Simulated Annealing 基于符号模拟和模拟退火的模拟电路设计优化
G. Gielen, H. Walscharts, W. Sansen
{"title":"Analog Circuit Design Optimization based on Symbolic Simulation and Simulated Annealing","authors":"G. Gielen, H. Walscharts, W. Sansen","doi":"10.1109/4.102664","DOIUrl":"https://doi.org/10.1109/4.102664","url":null,"abstract":"A methodology for the automatic design optimization of analog circuits is presented. A non-fixed topology approach is followed. A symbolic simulator, called ISAAC, generates an analytic AC model for any analog circuit, time-continuous or time-discrete, CMOS or bipolar. ISAAC's expressions can be fully symbolic or mixed numeric-symbolic, exact or simplified. The model is passed to the design optimization program OPTIMAN. For a user selected circuit topology, the independent design variables are automatically extracted and OPTIMAN sizes all elements to satisfy the performance constraints, thereby optimizing a user defined design objective. The optimization algorithm is simulated annealing. Practical examples show that OPTIMAN quickly designs analog circuits, closely meeting the specifications, and that it is a flexible and reliable design and exploration tool.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114699465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 272
A Highly Efficient Design System for Mixed Analog/Digital LSIs 一种高效的混合模拟/数字lsi设计系统
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468145
K. Maio, S.-I. Hayashi, M. Furihata, S. Ogura, Toshinori watanabe, M. Ishikawa
{"title":"A Highly Efficient Design System for Mixed Analog/Digital LSIs","authors":"K. Maio, S.-I. Hayashi, M. Furihata, S. Ogura, Toshinori watanabe, M. Ishikawa","doi":"10.1109/ESSCIRC.1989.5468145","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468145","url":null,"abstract":"An engineering system aimed to the highly efficient design of analog and/or mixed analog/digital custom LSIs is described. The system covers the areas of the system design using a new function level simulator, the circuit design and the layout by a circuit library and a layout library. The effectiveness of this engineering system is demonstrated through the design of a mixed analog/digital custom LSI for VCR use with about 5000 elements. This system has achieved the design efficiency of more than 1.5 times compared with the conventional methods.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116411186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信