亚微米CMOS差分通管逻辑的优化

ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI:10.1109/ESSCIRC.1989.5468086

J. Pasternak, C. Salama

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引用次数: 4

摘要

提出了显著提高CMOS差分通管逻辑(DPTL)速度的技术。利用DPTL的抗噪特性，可以减小信号摆幅，从而提高速度。提出了一种采用新型DPTL缓冲器的单相时钟方案。实验结果提供了在0.8微米CMOS技术中实现的DPTL除以N预分器(1¿N¿64)。

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Optimization of Submicron CMOS Differential Pass-Transistor Logic

Techniques for significantly enhancing the speed of CMOS differential pass-transistor logic (DPTL) are presented. Use is made of the noise immunity features of DPTL to enable signal swing reductions that result in increased speed. A novel single-phase clocking scheme using a new DPTL buffer is proposed. Experimental results are provided for a DPTL divide-by-N prescaler (1 ¿ N ¿ 64) implemented in a 0.8¿m CMOS technology.

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ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference

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