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ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference最新文献

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GrapMG: Cost-effective module generation 图1:高效的模块生成
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468187
H. Janssen, M. Treffers, R. Segers, J. Huisken
{"title":"GrapMG: Cost-effective module generation","authors":"H. Janssen, M. Treffers, R. Segers, J. Huisken","doi":"10.1109/ESSCIRC.1989.5468187","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468187","url":null,"abstract":"GrapMG is a module generator environment in which an IC-designer is able to make parametrized layout modules in a flexible way. With grapMG some very complex modules have been designed for use in a silicon compiler for digital signal processing chips. Successful application of module generation in this compiler is made possible because a new design strategy simplifies the adaptation of modules to other technologies. The investment in the development of new modules is small compared to traditional procedural methods. In this paper the design strategy is presented together with the facilities that are available in the module design environment.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122235176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
CASTOR: FSM Synthesis in a Digital Circuit Synthesis System 数字电路合成系统中的FSM合成
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468157
R. Amann, M. Neher, G. Rietsche, W. Rosenstiel, D. Schmid
{"title":"CASTOR: FSM Synthesis in a Digital Circuit Synthesis System","authors":"R. Amann, M. Neher, G. Rietsche, W. Rosenstiel, D. Schmid","doi":"10.1109/ESSCIRC.1989.5468157","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468157","url":null,"abstract":"Logic synthesis of digital systems can be divided into two different tasks: synthesis of the datapath and control synthesis. The Carlsruhe Digital Design System (CADDY) solves both tasks. Starting from a behavioral circuit description CADDY generates the structure of the datapath and a control graph (CG), which is the starting point for the synthesis of a finite state machine. In this paper we will concentrate on CASTOR, the FSM synthesis part in CADDY. It is well adapted to the properties of the internally generated contol graphs, but it is also a stand alone FSM synthesis system. We will first describe the FSM structure generator in CASTOR, then a new state assignment algorithm. Finally we will present our results for a standard benchmark set.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117298975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 500 nA 6th Order Bandpass S.C. Filter 一个500na的六阶带通S.C.滤波器
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468128
R. Castello, A. Grassi, S. Donati
{"title":"A 500 nA 6th Order Bandpass S.C. Filter","authors":"R. Castello, A. Grassi, S. Donati","doi":"10.1109/ESSCIRC.1989.5468128","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468128","url":null,"abstract":"A 6th order band-pass switched-capacitor (S.C.) filter that requires only 500 nA of total supply current has been designed and fabricated in a 2 ¿m CMOS technology. The filter is part of an implantable device powered by a ± 1.2 V battery, can drive up to 30 pF of capacitive load, and uses a 2 kHz master clock. Substantial reduction in the power consumption has been achieved by using a novel amplifier timesharing technique which allows to realize an arbitrary number of biquadratic cells with only ruo amplifiers. Further power saving was obtained with the use of positive feedback in the amplifier input stage to enhance its transconductance. The prototype chip requires an area of 2200 mils2.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114527807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
DTMF Generator based on Interleaved Oversampling 基于交错过采样的DTMF发生器
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468097
P. O'Leary, M. Pauritsch, F. Maloberti, Giampiero Raschetti
{"title":"DTMF Generator based on Interleaved Oversampling","authors":"P. O'Leary, M. Pauritsch, F. Maloberti, Giampiero Raschetti","doi":"10.1109/ESSCIRC.1989.5468097","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468097","url":null,"abstract":"A circuit is described which uses one oversampling frequency synthesizer in an interleaved mode to generate dual-tone multi-frequency (DTMF) telephone dialling tones. The synthesizer is based on direct digital synthesis using phase accumulation. The Digital to analogue conversion is carried out using a first order sigma-delta (¿¿). This ¿¿ converter is also used in interleaved mode. The smoothing filter consists of a simple second order RC filter.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122033206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Class AB CMOS Operational Amplifiers with Very High Efficiency 高效率的AB类CMOS运算放大器
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468139
L. Callewaert, W. Sansen
{"title":"Class AB CMOS Operational Amplifiers with Very High Efficiency","authors":"L. Callewaert, W. Sansen","doi":"10.1109/ESSCIRC.1989.5468139","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468139","url":null,"abstract":"A new, simple, yet very current efficient class AB amplifier principle is presented. When used as a differential input stage it features a settling time which is independent of the input signal, and a current efficiency superior to that of any conventional OTA. The same class AB stage can also be used as an output stage with a rail to rail output voltage swing, and a large drive capability. An amplifier with both input and output stages based on this new principle is presented. This amplifier features a gainbandwidth of 310 kHz and a settling time to 0.1% of 2.4 ¿s. It can drive a resistive load of 2500 Ohm in parallel with a capacitive load of 400 pF when operated on a 2.5V/-2.5V power supply, with a quiescent power consumption of only 285 ¿W.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116848159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Gate-Array Implementation of a DC-Motor Control System 直流电机控制系统的门阵列实现
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468205
H. Kerkhoff, M. van Bentem, E.A. de Boer
{"title":"A Gate-Array Implementation of a DC-Motor Control System","authors":"H. Kerkhoff, M. van Bentem, E.A. de Boer","doi":"10.1109/ESSCIRC.1989.5468205","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468205","url":null,"abstract":"A digital chip has been designed for a permanent-magnet DC motor control system based on pulse-width modulation techniques. The control system is used for cordless drilling and screwdriver machines. The system is implemented on a new, low latch-up susceptibility CMOS gate array.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"666 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134389183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A One Micron CMOS 160Mbit/s 8×8 Asynchronous Time Division Switch A 1微米CMOS 160Mbit/s 8×8异步时分开关
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468077
G. Surace, D. R. Clewett, A. Pickering
{"title":"A One Micron CMOS 160Mbit/s 8×8 Asynchronous Time Division Switch","authors":"G. Surace, D. R. Clewett, A. Pickering","doi":"10.1109/ESSCIRC.1989.5468077","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468077","url":null,"abstract":"This paper describes a CMOS self routing 8 input 8 output 160 Mbit/s switch chip designed on a one micron trench isolation technology and three layers of metal.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130526335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Highly Adaptive Rank Order Filter LSI for Two-Dimensional Video Signal Processing 用于二维视频信号处理的高自适应秩序滤波LSI
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468211
H. Kokubun, Kazuyuki Akechi, Kazumasa Kobayashi, M. Abe, T. Tajima, Satoru Omachi, Ki-ichi Kobayashi
{"title":"A Highly Adaptive Rank Order Filter LSI for Two-Dimensional Video Signal Processing","authors":"H. Kokubun, Kazuyuki Akechi, Kazumasa Kobayashi, M. Abe, T. Tajima, Satoru Omachi, Ki-ichi Kobayashi","doi":"10.1109/ESSCIRC.1989.5468211","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468211","url":null,"abstract":"A bit-sliced rank order filter LSI for real-time two-dimensional processing of TV video signals has been developed, fabricated by 2 um CMOS standard cell technology. The LSI architecture, suitable for real-time and adaptive processing and enabling the input word length to be easily expanded, is presented.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114988586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Analog CMOS Circuit for Mobile Radio Base Station Signal Processing 一种用于移动无线基站信号处理的模拟CMOS电路
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468096
P. Korhonen, Jukka Korhonen
{"title":"An Analog CMOS Circuit for Mobile Radio Base Station Signal Processing","authors":"P. Korhonen, Jukka Korhonen","doi":"10.1109/ESSCIRC.1989.5468096","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468096","url":null,"abstract":"This paper describes an analog CMOS circuit for NMT-450 and NMT-900 mobile radio base station signal processing. The circuit includes receive and transmit audio filters, a deviation limiter (AGC and hardlimiter) and two level detectors, all implemented with switching capacitor technology. Measurement results show that strict performance requirements for SNR and filter responses are met regardless of the great number of successive SC- stages.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"378 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122772811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A New Carry Free Division Algorithm and Application to a Single Chip 1024 bits RSA Processor 一种新的免进位除法算法及其在单片1024位RSA处理器上的应用
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468076
A. Vandemeulebroecke, E. Vanzieleghem, T. Denayer, C. Trullemans, P. Jespers
{"title":"A New Carry Free Division Algorithm and Application to a Single Chip 1024 bits RSA Processor","authors":"A. Vandemeulebroecke, E. Vanzieleghem, T. Denayer, C. Trullemans, P. Jespers","doi":"10.1109/ESSCIRC.1989.5468076","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468076","url":null,"abstract":"A new carry-free division algorithm will be described; it is based on the properties of RSD arithmetic to avoid carry propagation. Its application to a 1024 bits RSA cryptographic chip will also be presented. Thanks to the features of this new algorithm, high performance (8 kbits/s for 1024 bits words) was obtained for relatively small area and power consumption (80 mm2 in a 2 ¿m CMOS process and 500 mW at 25 MHz).","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127224240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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