D. Schmitt-Landsiedel, B. Hoppe, G. Neuendorf, M. Wurm, J. Winnerl
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Pipelined 16k Buffer RAM with 300MHz Operating Frequency
A new pipeline architecture for fast CMOS buffer SRAMs is presented that allows operation at very high clock rates. The high speed is achieved by use of a hierarchical architecture and a memory cell with separate read and write data lines.
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