Optimization of Submicron CMOS Differential Pass-Transistor Logic

Abstract

Techniques for significantly enhancing the speed of CMOS differential pass-transistor logic (DPTL) are presented. Use is made of the noise immunity features of DPTL to enable signal swing reductions that result in increased speed. A novel single-phase clocking scheme using a new DPTL buffer is proposed. Experimental results are provided for a DPTL divide-by-N prescaler (1 ¿ N ¿ 64) implemented in a 0.8¿m CMOS technology.