The Design of Scaled-Down Submicron 1Mb ECL/TTL BiCMOS SRAMs

Abstract

INTRODUCTION BiCMOS scalability problem is considered to be serious in submicron generation devices because BiCMOS combination logic gates lose their speed advantage to CMOS logic gates as an external supply voltage is scaled-down to 3.3V [1], Actually for CMOS logic gates, external 3.3V supply voltage has various merits in the light of hot-carrier induced MOSFET degradation, time-dependent dielectric breakdown (TDDB) of gate oxide, power-reduction and so on. However, it is disadvantageous that 3.3V supply voltage devices are not compatible to former generation devices of 5V power supply. This paper will describe 5V-only BiCMOS SRAM architecture covering from 0.8jim to 0.5|im design rules and its application to lM-bit ECL/TTL SRAMs [2,3]. Two-way BiCMOS internal voltage supply, together with newly developed interface circuits, prevents MOSFET gate-drain voltage exceeding breakdown voltage to assure MOSFET reliability, and can optimize the oxide thickness so as to minimize the gate delay.