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ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference最新文献

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Design and Evaluation of an Integrated Digital-Analogue Filter Converter 一种集成数模滤波器转换器的设计与评价
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468163
J. Vital, J. Franca, F. Maloberti
{"title":"Design and Evaluation of an Integrated Digital-Analogue Filter Converter","authors":"J. Vital, J. Franca, F. Maloberti","doi":"10.1109/ESSCIRC.1989.5468163","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468163","url":null,"abstract":"This paper describes the design, integrated circuit implementation, and experimental evaluation of a novel building block that realizes the combined operations of digital-analogue conversion and FIR filtering (DAFIC). To maximize the advantages of both digital and analogue techniques, the circuit comprises a 4-stage digital delay line providing the input to 4 8-bit algorithmic digital-analogue converters whose gains are weighted according to the coefficients of an FIR filtering function. The circuit was implemented using a 3¿ Single-Metal/Double-Poly CMOS process. Experimental results obtained from prototype chips are in good agreement with the expected theoretical behaviour of this novel building block.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114239442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 24-Bit Block Floating Point Digital Signal Processor 一个24位块浮点数字信号处理器
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468219
G. Dixon, T. Heighway, J. Fox, D. Wadham, L. Williams
{"title":"A 24-Bit Block Floating Point Digital Signal Processor","authors":"G. Dixon, T. Heighway, J. Fox, D. Wadham, L. Williams","doi":"10.1109/ESSCIRC.1989.5468219","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468219","url":null,"abstract":"A CMOS 24-bit Block Floating Point Digital Signal Processor chip for Sonar applications is described. The device integrates data and program memory, two arithmetic processing elements, and address generator in a single chip providing a performance improvement of up to ten times that available using standard DSP devices for Sonar signal processing. The device has been implemented on a 1.4 micron two layer metal CMOS process.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131892553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A sub 2ns ECL to CMOS level converter in 1μm BiCMOS technology 采用1μm BiCMOS技术的2ns ECL - CMOS电平转换器
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468116
E. Mullner, R. Krebs, I. Ruge
{"title":"A sub 2ns ECL to CMOS level converter in 1μm BiCMOS technology","authors":"E. Mullner, R. Krebs, I. Ruge","doi":"10.1109/ESSCIRC.1989.5468116","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468116","url":null,"abstract":"A new circuit for level conversion in BiCMOS technology is proposed in this paper. This circuit converts signals from an ECL environment using a bipolar voltage controlled current source followed by a CMOS current controlled voltage source. This scheme provides both high speed and low sensitivity to parameter variation at a moderate power consumption. Simulation shows, that delaytimes less than 2ns in a 1μm technology can be achieved for loads of 500fF at a power consumption of 5mW.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114806812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 3μm-CMOS Analogue Audio Circuit for Mobile Telephone Application 一种3μm cmos手机模拟音频电路
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468091
Gebhard Meicher, Francisco Guerrero, Hannes Barnthaler, K. Ilzer, D. Strle, M. Groenroos
{"title":"A 3μm-CMOS Analogue Audio Circuit for Mobile Telephone Application","authors":"Gebhard Meicher, Francisco Guerrero, Hannes Barnthaler, K. Ilzer, D. Strle, M. Groenroos","doi":"10.1109/ESSCIRC.1989.5468091","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468091","url":null,"abstract":"An analogue IC for mobile telephone application (Handset IC) is presented. The circuit performs the analogue functions required for the speech channels (low noise microphone amplifier, earphone driver for 130 nF load, sidetone buffer, transmit line driver, speaker line drivers, variable gain-loss stage) and DTMF generation. A buzzer driver has also been integrated for general purpose system signalling. A watchdog circuit supervises the correct functioning of the microprocessor. Common time-continuous and switch-capacitor techniques have been used to minimize the number of external components. The above functions have been implemented in a manner that fulfills the standards NMT DOC.900-3 incl. addendum, NMT DOC.450-3, BABT/SITS/84/13/Aincl. addendums, and EIAIS-19-A. The circuit has been integrated in a standard 3μm-CMOS double-poly single-metal process and requires 26.4 mm2.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123949518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Analog-Oriented Routing Tool for CMOS Analog Integrated Circuits 面向模拟的CMOS模拟集成电路布线工具
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468182
S. Piguet, F. Rahali, M. Declercq, M. Kayal
{"title":"An Analog-Oriented Routing Tool for CMOS Analog Integrated Circuits","authors":"S. Piguet, F. Rahali, M. Declercq, M. Kayal","doi":"10.1109/ESSCIRC.1989.5468182","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468182","url":null,"abstract":"The performance of analog ICs strongly depends on layout characteristics. After identifying the various categories of placement and routing constraints, this paper describes a routing strategy dedicated to take into account those specific analog features. Working in close coordination with an analog placement tool, the new routing tool uses global and local routing techniques that can handle the various constraints. It uses intelligent path scheduling and multi-constrained path minimization with electrical extraction capabilities. The selection of some routing options can be controlled by an expert system. The aim of the router is to be as close as possible to a designer's routing style. Results of automated analog layouts are presented.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124218434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Race-Free Clocking of CMOS Pipelines through a Single Global Clock 通过单个全局时钟实现CMOS流水线的无竞争时钟
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/4.102674
C. H. Lau, D. Renshaw
{"title":"Race-Free Clocking of CMOS Pipelines through a Single Global Clock","authors":"C. H. Lau, D. Renshaw","doi":"10.1109/4.102674","DOIUrl":"https://doi.org/10.1109/4.102674","url":null,"abstract":"To ease global clock distribution in a synchronous system extending over several levels of interconnect (for example between logic blocks within a chip, chips mounted on a printed circuit board and boards of chips across a backplane), a race-free clocking scheme for CMOS VLSI requiring a single clock line is presented. Since the technique is race-free, the clock line may be driven by a sinusoid, thereby avoiding the transmission of the higher frequency components associated with fast clock edges. In this way, clock signal distortion due to transmission line effects will be kept to a minimum.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"251 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116517147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A Single Power Supply 10Bit Video Bi-CMOS Sample-and-Hold IC 单电源10Bit视频双cmos采样保持IC
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468175
K. Tsugaru, M. Noda, Y. Sugimoto, Takao Itoh, Y. Suwa
{"title":"A Single Power Supply 10Bit Video Bi-CMOS Sample-and-Hold IC","authors":"K. Tsugaru, M. Noda, Y. Sugimoto, Takao Itoh, Y. Suwa","doi":"10.1109/ESSCIRC.1989.5468175","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468175","url":null,"abstract":"A new single power supply 10bit video Bi-CMOS sample-and-hold IC is described. High speed, low power and high-accuracy sample-and-hold operation has been achieved using the complementary connected buffer type sample switch. The equivalent PNP transistor is formed by the combination of NPN and PMOS transistors. The sample-and-hold IC has been implemented in 1.2um Bi-CMOS technology. The acquisition time and the switching settling time are 20ns and 15ns, respectively. It works with +5V single power supply and the power dissipation is 150mW.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122310363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Noise Considerations on High Density DRAMs: Problems and Solutions 高密度dram的噪声考虑:问题与解决方案
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468200
B. Murphy, F. Bonner, J. Stecker, W. Reczek, W. Pribyl, J. Harter
{"title":"Noise Considerations on High Density DRAMs: Problems and Solutions","authors":"B. Murphy, F. Bonner, J. Stecker, W. Reczek, W. Pribyl, J. Harter","doi":"10.1109/ESSCIRC.1989.5468200","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468200","url":null,"abstract":"On-chip generated noise limits further miniaturization of DRAMs. The basis for consideration is a model including the effects of ohmic voltage drop and bond wire inductances. SPICE simulations are used to study the performance that results from chip architecture, circuit placement and circuit design. The results are verified by experimental data.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123086643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Multilevel Design and Verification of Hardware/Software Systems 硬件/软件系统的多级设计和验证
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/4.102665
L. Philipson
{"title":"Multilevel Design and Verification of Hardware/Software Systems","authors":"L. Philipson","doi":"10.1109/4.102665","DOIUrl":"https://doi.org/10.1109/4.102665","url":null,"abstract":"It is pointed out that most real systems in information technology are based on cooperating hardware and software, and the hardware is more than a single chip. System design can be viewed as a massively multidimensional optimization problem for which the solution set is only partially known. Experimental exploration of the design space is the only available approach. A number of projects carried out at Lund University demonstrate that a dramatic increase in system performance and design productivity can be gained. The approach includes a new attitude to the design process, a new role for the designer, new design methodology, and new concepts. It has been shown that, by making extensive use of modern tools, the designer can develop and evaluate a set of hierarchical functional models of the entire system during the design process and establish well-defined relationships between the models. >","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122048127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Silicon Clock Recovery IC's for 2 to 3.5 Gbit/s 硅时钟恢复IC为2至3.5 Gbit/s
ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI: 10.1109/ESSCIRC.1989.5468062
Z. Wang, U. Langmann, B. Bosch
{"title":"Silicon Clock Recovery IC's for 2 to 3.5 Gbit/s","authors":"Z. Wang, U. Langmann, B. Bosch","doi":"10.1109/ESSCIRC.1989.5468062","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1989.5468062","url":null,"abstract":"A novel clock recovery IC for Gbit/s optical communication is presented, employing a 1:2 dynamic frequency divider scheme with an external resonator filter. It is based on a conventional Si bipolar process. Two versions of the same IC design are presented, one optimized for 2 to 3 Gbit/s, the other for 3 to 4 Gbit/s. Clock recovery is demonstrated at 2.23 and 3.52 Gbit/s, leading to clock signals of 1.115 and 1.76 GHz, respectively. Measured rms clock phase jitter is less than 0.3°.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132012931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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