G. Dixon, T. Heighway, J. Fox, D. Wadham, L. Williams
{"title":"一个24位块浮点数字信号处理器","authors":"G. Dixon, T. Heighway, J. Fox, D. Wadham, L. Williams","doi":"10.1109/ESSCIRC.1989.5468219","DOIUrl":null,"url":null,"abstract":"A CMOS 24-bit Block Floating Point Digital Signal Processor chip for Sonar applications is described. The device integrates data and program memory, two arithmetic processing elements, and address generator in a single chip providing a performance improvement of up to ten times that available using standard DSP devices for Sonar signal processing. The device has been implemented on a 1.4 micron two layer metal CMOS process.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 24-Bit Block Floating Point Digital Signal Processor\",\"authors\":\"G. Dixon, T. Heighway, J. Fox, D. Wadham, L. Williams\",\"doi\":\"10.1109/ESSCIRC.1989.5468219\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A CMOS 24-bit Block Floating Point Digital Signal Processor chip for Sonar applications is described. The device integrates data and program memory, two arithmetic processing elements, and address generator in a single chip providing a performance improvement of up to ten times that available using standard DSP devices for Sonar signal processing. The device has been implemented on a 1.4 micron two layer metal CMOS process.\",\"PeriodicalId\":187183,\"journal\":{\"name\":\"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1989.5468219\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1989.5468219","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 24-Bit Block Floating Point Digital Signal Processor
A CMOS 24-bit Block Floating Point Digital Signal Processor chip for Sonar applications is described. The device integrates data and program memory, two arithmetic processing elements, and address generator in a single chip providing a performance improvement of up to ten times that available using standard DSP devices for Sonar signal processing. The device has been implemented on a 1.4 micron two layer metal CMOS process.