B. Murphy, F. Bonner, J. Stecker, W. Reczek, W. Pribyl, J. Harter
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Noise Considerations on High Density DRAMs: Problems and Solutions
On-chip generated noise limits further miniaturization of DRAMs. The basis for consideration is a model including the effects of ohmic voltage drop and bond wire inductances. SPICE simulations are used to study the performance that results from chip architecture, circuit placement and circuit design. The results are verified by experimental data.