{"title":"采用1μm BiCMOS技术的2ns ECL - CMOS电平转换器","authors":"E. Mullner, R. Krebs, I. Ruge","doi":"10.1109/ESSCIRC.1989.5468116","DOIUrl":null,"url":null,"abstract":"A new circuit for level conversion in BiCMOS technology is proposed in this paper. This circuit converts signals from an ECL environment using a bipolar voltage controlled current source followed by a CMOS current controlled voltage source. This scheme provides both high speed and low sensitivity to parameter variation at a moderate power consumption. Simulation shows, that delaytimes less than 2ns in a 1μm technology can be achieved for loads of 500fF at a power consumption of 5mW.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A sub 2ns ECL to CMOS level converter in 1μm BiCMOS technology\",\"authors\":\"E. Mullner, R. Krebs, I. Ruge\",\"doi\":\"10.1109/ESSCIRC.1989.5468116\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new circuit for level conversion in BiCMOS technology is proposed in this paper. This circuit converts signals from an ECL environment using a bipolar voltage controlled current source followed by a CMOS current controlled voltage source. This scheme provides both high speed and low sensitivity to parameter variation at a moderate power consumption. Simulation shows, that delaytimes less than 2ns in a 1μm technology can be achieved for loads of 500fF at a power consumption of 5mW.\",\"PeriodicalId\":187183,\"journal\":{\"name\":\"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1989.5468116\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1989.5468116","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A sub 2ns ECL to CMOS level converter in 1μm BiCMOS technology
A new circuit for level conversion in BiCMOS technology is proposed in this paper. This circuit converts signals from an ECL environment using a bipolar voltage controlled current source followed by a CMOS current controlled voltage source. This scheme provides both high speed and low sensitivity to parameter variation at a moderate power consumption. Simulation shows, that delaytimes less than 2ns in a 1μm technology can be achieved for loads of 500fF at a power consumption of 5mW.
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