Noise Considerations on High Density DRAMs: Problems and Solutions

ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI:10.1109/ESSCIRC.1989.5468200

B. Murphy, F. Bonner, J. Stecker, W. Reczek, W. Pribyl, J. Harter

引用次数: 1

Abstract

On-chip generated noise limits further miniaturization of DRAMs. The basis for consideration is a model including the effects of ohmic voltage drop and bond wire inductances. SPICE simulations are used to study the performance that results from chip architecture, circuit placement and circuit design. The results are verified by experimental data.

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高密度dram的噪声考虑:问题与解决方案

片上产生的噪声限制了dram的进一步小型化。考虑的基础是一个包括欧姆压降和键合线电感影响的模型。SPICE模拟用于研究芯片结构、电路布局和电路设计对性能的影响。实验数据验证了所得结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference

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