{"title":"硅时钟恢复IC为2至3.5 Gbit/s","authors":"Z. Wang, U. Langmann, B. Bosch","doi":"10.1109/ESSCIRC.1989.5468062","DOIUrl":null,"url":null,"abstract":"A novel clock recovery IC for Gbit/s optical communication is presented, employing a 1:2 dynamic frequency divider scheme with an external resonator filter. It is based on a conventional Si bipolar process. Two versions of the same IC design are presented, one optimized for 2 to 3 Gbit/s, the other for 3 to 4 Gbit/s. Clock recovery is demonstrated at 2.23 and 3.52 Gbit/s, leading to clock signals of 1.115 and 1.76 GHz, respectively. Measured rms clock phase jitter is less than 0.3°.","PeriodicalId":187183,"journal":{"name":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Silicon Clock Recovery IC's for 2 to 3.5 Gbit/s\",\"authors\":\"Z. Wang, U. Langmann, B. Bosch\",\"doi\":\"10.1109/ESSCIRC.1989.5468062\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel clock recovery IC for Gbit/s optical communication is presented, employing a 1:2 dynamic frequency divider scheme with an external resonator filter. It is based on a conventional Si bipolar process. Two versions of the same IC design are presented, one optimized for 2 to 3 Gbit/s, the other for 3 to 4 Gbit/s. Clock recovery is demonstrated at 2.23 and 3.52 Gbit/s, leading to clock signals of 1.115 and 1.76 GHz, respectively. Measured rms clock phase jitter is less than 0.3°.\",\"PeriodicalId\":187183,\"journal\":{\"name\":\"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1989.5468062\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1989.5468062","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel clock recovery IC for Gbit/s optical communication is presented, employing a 1:2 dynamic frequency divider scheme with an external resonator filter. It is based on a conventional Si bipolar process. Two versions of the same IC design are presented, one optimized for 2 to 3 Gbit/s, the other for 3 to 4 Gbit/s. Clock recovery is demonstrated at 2.23 and 3.52 Gbit/s, leading to clock signals of 1.115 and 1.76 GHz, respectively. Measured rms clock phase jitter is less than 0.3°.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
