Stephen D. Levy, P. Hurst, P. Ju, J. Huggins, C. R. Cole
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引用次数: 0
摘要
本文将描述一种采用3.6 m Si栅极CMOS工艺实现的单片2400 bps调制解调器。集成电路包括模拟前端(AFE)和数字信号处理器(DSP)，发送端和部分接收端信号处理在模拟域进行。DSP专用于接收信号处理——时序恢复、自适应均衡、载波恢复/解调和解码。该芯片使用单个5v电源，占地68.8 mm2，功耗120mw。本文将介绍该集成电路的设计和性能。
A single-chip 2400 bps modem which has been implemented in a 3.6 ¿m Si gate CMOS process will be described. An analog front end (AFE) and digital signal processor (DSP) are included on the IC. The transmit-side and part of the receive-side signal processing are performed in the analog domain. The DSP is dedicated to receive signal processing - timing recovery, adaptive equalization, carrier recovery/demodulation and decoding. The chip operates off a single 5 V supply, occupies 68.8 mm2 and dissipates 120 mW. The design and performance of the IC will be presented.
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