A Single Chip 5 Volt 2400 Bps Modem

ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI:10.1109/ESSCIRC.1989.5468101

Stephen D. Levy, P. Hurst, P. Ju, J. Huggins, C. R. Cole

引用次数: 0

Abstract

A single-chip 2400 bps modem which has been implemented in a 3.6 ¿m Si gate CMOS process will be described. An analog front end (AFE) and digital signal processor (DSP) are included on the IC. The transmit-side and part of the receive-side signal processing are performed in the analog domain. The DSP is dedicated to receive signal processing - timing recovery, adaptive equalization, carrier recovery/demodulation and decoding. The chip operates off a single 5 V supply, occupies 68.8 mm2 and dissipates 120 mW. The design and performance of the IC will be presented.

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单片5伏2400 Bps调制解调器

本文将描述一种采用3.6 m Si栅极CMOS工艺实现的单片2400 bps调制解调器。集成电路包括模拟前端(AFE)和数字信号处理器(DSP)，发送端和部分接收端信号处理在模拟域进行。DSP专用于接收信号处理——时序恢复、自适应均衡、载波恢复/解调和解码。该芯片使用单个5v电源，占地68.8 mm2，功耗120mw。本文将介绍该集成电路的设计和性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference

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