逻辑综合中的并行分解

ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference Pub Date : 1989-09-01 DOI:10.1109/ESSCIRC.1989.5468151

Krzysztof Jasinski, Tadeusz kuba, J. Kalinowski

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引用次数: 12

摘要

本文提出了一种基于并行分解的VLSI设计中逻辑综合的新方法。我们的想法是使用一种有效的方法进行多输出函数约简，以选择在最终实现中产生最小硅面积的分解。给出了该合成方法的实验结果和评价。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Parallel Decomposition in Logic Synthesis

In this paper a new approach to logic synthesis in VLSI design, based on parallel decomposition, is proposed. The idea is to use an effective method for multiple-output function reduction to select a decomposition that yields minimal silicon area in the final implementation. Experimental results and assessment of this synthesis method are provided.

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ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference

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