Microelectronic Engineering最新文献

{"title":"Low-Temperature Wafer-Level Bonding with Cu-Sn-In Solid Liquid Interdiffusion for Microsystem Packaging","authors":"Obert Golim ,&nbsp;Vesa Vuorinen ,&nbsp;Tobias Wernicke ,&nbsp;Marta Pawlak ,&nbsp;Mervi Paulasto-Kröckel","doi":"10.1016/j.mee.2024.112140","DOIUrl":"10.1016/j.mee.2024.112140","url":null,"abstract":"<div><p>This work demonstrates the potential use of Cu-Sn-In metallurgy for wafer-level low-temperature solid-liquid interdiffusion (LT-SLID) bonding process for microelectromechanical system (MEMS) packaging. Test structures containing seal-ring shaped SLID bonds were employed to bond silicon and glass wafers at temperatures as low as 170 °C. Scanning acoustic microscopy (SAM) was utilized to inspect the quality of as-bonded wafers. The package hermeticity was characterized by cap-deflection measurements and evaluated through finite element modelling. The results indicate the bonds are hermetic, but residual stresses limit the quantitative analysis of the hermeticity. The microstructural studies confirm the bonds contain a single-phase intermetallic Cu₆(Sn,In)₅ that remains thermally stable up to 500 °C. This work shows Cu-Sn-In based low-temperature bonding method as a viable packaging option for optical MEMS or other temperature-sensitive components.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0167931724000091/pdfft?md5=0fe77f405f98dca2b39eb4fe43d13641&pid=1-s2.0-S0167931724000091-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139507284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Engineering TiOx interlayers in high vacuum for Al-contacted MoSe2 transistors","authors":"Yoobin Oh,&nbsp;Youngho Jo,&nbsp;Woong Choi","doi":"10.1016/j.mee.2024.112139","DOIUrl":"10.1016/j.mee.2024.112139","url":null,"abstract":"<div><p>We present an enhanced performance of MoSe₂ transistors via sequentially depositing Ti and Al in high vacuum to establish TiO_x<span> interlayers positioned between the MoSe</span>₂<span> channel and Ti/Al contacts. Transmission electron microscopy analysis revealed the presence of TiO</span>_x at the MoSe₂/Ti interface. While MoSe₂ transistors exhibited poor device performance in the absence of a TiO_x interlayer, the introduction of a TiO_x interlayer yielded a notable transistor performance, including an on/off ratio of ∼10⁵, a field-effect mobility of ∼40 cm² V⁻¹ s⁻¹<span>, and a contact resistance of ∼100 kΩ μm. These enhancements were attributed to the beneficial effects of Fermi level unpinning and interfacial doping facilitated by TiO</span>_x interlayers. These results underscore the feasibility of incorporating TiO_x interlayers to enable the use of conventional Al contacts in MoSe₂<span> transistors, delivering significant implications for enhancing the performance of transition metal dichalcogenide transistors.</span></p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-01-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139423259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ta/Al/CuW low temperature ohmic contacts for GaN-on-Si HEMT","authors":"Zijing Xie ,&nbsp;Nianhe Xiong ,&nbsp;Jun Tang ,&nbsp;Hong Wang","doi":"10.1016/j.mee.2024.112132","DOIUrl":"10.1016/j.mee.2024.112132","url":null,"abstract":"<div><p><span>We proposed a low temperature Au-free ohmic contacts<span><span> of GaN-on-Si HEMT with the Ta/Al/CuW metal stack. The CuW was deposited by using the dual-target </span>magnetron<span><span> sputter deposition method<span>. The annealing conditions and recess depth of ohmic area were systematically investigated. By utilizing the Ta/Al/CuW structure, an improved contact characteristic (0.49 Ω·mm) is obtained following annealing at 550 °C for 10 min in vacuum, with the recess depth of 30 nm(±2 nm). This performance surpasses that of Ta/Al/W Au-free contacts (1.07 Ω·mm). Furthermore, both the Ta/Al/CuW ohmic contacts (RMS = 6.3 nm) and the Ta/Al/W ohmic contacts (RMS = 6.0 nm) exhibit smooth surface morphology. Compared to Ti contact layer, Ta demonstrates superior performance in low temperature contact and breakdown test. </span></span>Amorphous Ta layer can effectively suppress Cu </span></span></span>diffusion. The GaN-on-Si HEMT was also fabricated based on Ta/Al/CuW Au-free ohmic contacts, exhibiting excellent DC characteristics.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139104004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Aptasensors based on silicon nanowire field-effect transistors for electrical detection of thrombin","authors":"Rony Midahuen ,&nbsp;Valérie Stambouli ,&nbsp;Caroline Fontelaye ,&nbsp;Guillaume Nonglaton ,&nbsp;Nicolas Spinelli ,&nbsp;Sylvain Barraud","doi":"10.1016/j.mee.2023.112130","DOIUrl":"10.1016/j.mee.2023.112130","url":null,"abstract":"<div><p><span>Arrays of silicon<span><span> nanowire field-effect transistors (Si NWFETs) were built to detect thrombin (a model biomarker) electrically. The Si NWFETs were created using a conventional top-down CMOS process, allowing them to be co-integrated with CMOS </span>readout circuits<span> in the future. EHTES organosilane was then used to graft aptamer probes onto the HfO</span></span></span>₂<span><span> gate oxide<span> of Si nanowires. We investigated the influence of aptamer grafting and thrombin recognition on the electrical transfer capabilities of Si NWFET </span></span>aptasensors<span> in details. Our technique was evaluated on a significant number of Si NWFETs, including two distinct chips with 30 aptasensors apiece. According to the findings, aptamer grafting increased the threshold voltage by a positive range of +28.8 mV to +87.7 mV, depending on the aptasensor employed. Thrombin identification, on the other hand, resulted in a negative shift of the threshold voltage between −26.6 and − 23.8 mV. These opposing voltage shifts coincide with the aptamer probes' and thrombin molecules' electric charges, respectively. These findings provide unique demonstration of Si NWFETs manufactured utilizing typical top-down CMOS processing methods, allowing these devices to be used in various biomedical and biosensing applications.</span></span></p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139068987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Relaxation effects on the structural and piezoelectric properties of wurtzite ZnS and CdS thin films under in-plane strain","authors":"Dongsheng Wang ,&nbsp;Xuewen Li ,&nbsp;Guoqiang Qin","doi":"10.1016/j.mee.2023.112131","DOIUrl":"10.1016/j.mee.2023.112131","url":null,"abstract":"<div><p><span><span><span>Through first-principles investigations, we examine variations in the atomic crystal structure<span>, thermal stability, electronic structure, and piezoelectric properties of </span></span>wurtzite ZnS and CdS under in-plane strain. We specifically aim to elucidate the distinct effects arising from two relaxation modes: elastic and non-elastic. Our analyses reveal that the in-plane strain-induced </span>deformation behaviors<span> and performance changes in these sulfides are remarkably similar, attributable to the similar atomic arrangements<span>, anionic sulfur elements, and analogous cation electronic configurations. However, following non-elastic relaxation, enhanced robustness emerges in the lattice volume and chemical bonding, alongside stronger thermal stability and attenuated modifications in the piezoelectric coefficient. We posit that these marked discrepancies from elastic relaxation may originate from subtle differences in the electronegativities and </span></span></span><em>d</em>-orbital electron configurations between the Zn²⁺ and Cd²⁺ cations. By offering fundamental new insights into the atomic-scale relaxation phenomena in wurtzite binaries, this work significantly furthers the fundamental understanding of structure-property relationships in these materials. Moreover, delineating the precise impacts of elastic versus non-elastic relaxation serves as an effective tuning methodology to engineer the piezoelectric and electronic traits of sulfide compounds for cutting-edge applications.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139068746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel time-domain in-memory computing unit using STT-MRAM","authors":"Ankana Saha ,&nbsp;Srija Alla ,&nbsp;Vinod Kumar Joshi","doi":"10.1016/j.mee.2023.112128","DOIUrl":"10.1016/j.mee.2023.112128","url":null,"abstract":"<div><p>Advancements in technologies like Big Data, IoT, and AI have revealed a bottleneck in traditional von-Neumann architecture, resulting in high energy consumption and limited memory bandwidth. In-memory computing (IMC) presents a promising solution by enabling computations directly within the memory, enhancing energy-efficient computing. The existing time-domain (TD)-based IMC computations either require multiple cycles for computation through a successive read/write approach or contribute to the complexity of the peripheral circuit by adopting a cumulative delay approach. In this paper, we present a novel array architecture that utilizes spin transfer torque magnetic random access memory (STT-MRAM) bit-cells, mitigating source degeneration issue. By leveraging this advanced technology and employing a TD computing scheme, we have successfully implemented various arithmetic operations, alongside a comprehensive set of Boolean logic operations. Our design demonstrates improved area and energy efficiency compared to other existing TD computing schemes. Furthermore, despite the higher delay, our parameter-driven optimization approach efficiently minimizes it. To validate our proposal, we performed simulations using the 45 nm CMOS process and the Verilog-A based magnetic tunnel junction (MTJ) compact model. Through meticulous Monte-Carlo simulations, considering CMOS variations, the results demonstrate enhanced computational accuracy with increasing Tunnel Magnetoresistance (TMR) ratio, showcasing the potential of our architecture in advancing the field of computing.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0167931723001934/pdfft?md5=4a658dba1e04ea314158b471fb5565e5&pid=1-s2.0-S0167931723001934-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139026476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel time-domain in-memory computing unit using STT-MRAM","authors":"Ankana Saha, Srija Alla, Vinod Kumar Joshi","doi":"10.1016/j.mee.2023.112128","DOIUrl":"https://doi.org/10.1016/j.mee.2023.112128","url":null,"abstract":"<p>Advancements in technologies like Big Data, IoT, and AI have revealed a bottleneck in traditional von-Neumann architecture, resulting in high energy consumption and limited memory bandwidth. In-memory computing (IMC) presents a promising solution by enabling computations directly within the memory, enhancing energy-efficient computing. The existing time-domain (TD)-based IMC computations either require multiple cycles for computation through a successive read/write approach or contribute to the complexity of the peripheral circuit by adopting a cumulative delay approach. In this paper, we present a novel array architecture that utilizes spin transfer torque magnetic random access memory (STT-MRAM) bit-cells, mitigating source degeneration issue. By leveraging this advanced technology and employing a TD computing scheme, we have successfully implemented various arithmetic operations, alongside a comprehensive set of Boolean logic operations. Our design demonstrates improved area and energy efficiency compared to other existing TD computing schemes. Furthermore, despite the higher delay, our parameter-driven optimization approach efficiently minimizes it. To validate our proposal, we performed simulations using the 45 nm CMOS process and the Verilog-A based magnetic tunnel junction (MTJ) compact model. Through meticulous Monte-Carlo simulations, considering CMOS variations, the results demonstrate enhanced computational accuracy with increasing Tunnel Magnetoresistance (TMR) ratio, showcasing the potential of our architecture in advancing the field of computing.</p>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139029357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simulation study of three-dimensional grayscale ice lithography on amorphous solid water for blazed gratings","authors":"Jinyu Guo ,&nbsp;Shuoqiu Tian ,&nbsp;Wentao Yuan ,&nbsp;Xujie Tong ,&nbsp;Rui Zheng ,&nbsp;Shan Wu ,&nbsp;Ding Zhao ,&nbsp;Yifang Chen ,&nbsp;Min Qiu","doi":"10.1016/j.mee.2023.112129","DOIUrl":"10.1016/j.mee.2023.112129","url":null,"abstract":"<div><p><span><span>Electron beam lithography (EBL) on </span>amorphous<span> solid water (ASW), termed as ice lithography (IL), has demonstrated promising capability in pattern transfer with unique advantages such as reduced proximity effect<span>. So far, ice lithography for binary patterning has been proved a great success, however, application for three-dimensional (3D) profiling in nanoscale<span> has still not been addressed to the best of our knowledge. This paper reports, for the first time, our progress in simulating study of three-dimensional ice lithography on ASW for linear blazed gratings, aiming to overcome the difficulty in replicating high quality blazed gratings with high diffraction efficiency. Systematic simulation of </span></span></span></span>grayscale<span> ice lithography for 3-D blazed grating templates with desired surface quality as the task was carried out, using Monte Carlo algorithm based on the measured contrast curves of ASW. For comparison, grayscale electron beam lithography on PMMA was also performed. The resultant profiles of blazed wavelengths around 1550 nm by grayscale IL show less flaws and higher diffraction efficiencies than by EBL. The successful simulation of 3D grayscale IL provides us with instructive guide for the fabrication of 3D nanostructures as a whole through the grayscale ice lithography on ASW.</span></p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138693085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Self-powered motion state monitoring system based on combined triboelectric nanogenerators for human physiological signal monitoring and energy collection","authors":"Liangsong Huang,&nbsp;Xiaofei Bu,&nbsp;Peng Zhang,&nbsp;Kun Zhang,&nbsp;Yuxia Li,&nbsp;Dengxu Wang,&nbsp;Chao Ding","doi":"10.1016/j.mee.2023.112127","DOIUrl":"10.1016/j.mee.2023.112127","url":null,"abstract":"<div><p><span>The study of self-powered motion state monitoring systems based on triboelectric nanogenerators has recently received increasing attention. In this paper, we propose a self-powered system consisting of two low-cost and simply manufactured triboelectric nanogenerators for human </span>physiological signal<span><span> monitoring and energy collection. This system can monitor the trunk information and gait information during human activities, and measure </span>human motion<span><span> status in a holistic manner. The triboelectric nanogenerator, which monitors body torso information (B-TENG), we optimize its triboelectric layer through the microstructure of sandpaper to increase its contact area with the skin. In addition, by adding iron powder into the B-TENG electrode layer, the magnetic permeability of the induction electrode is increased to improve its output performance, and its maximum open-circuit voltage can reach 44.3 V. The triboelectric nanogenerator, which is installed on the foot to monitor gait information (F-TENG), can reach an average open-circuit voltage of 205.6 V by adding a rectangular protrusion structure to the triboelectric layer. In addition, due to its high output performance (∼4700 μw), the F-TENG can collect mechanical energy generated from the soles of the feet during daily human activities and charge a 100 μF capacitor to 1.4 V within 60 s, subsequently powering the miniature electronics. During foot walking, F-TENG is able to light up more than 60 light-emitting diodes. By having the experimenters wear these two triboelectric nanogenerators, we can record the frequency and amplitude signals of the experimenter's elbow, knee, breath, and gait in real time. We also monitored three running states of the human body through these two triboelectric nanogenerators, including normal state, insufficient exercise capacity, and dyspnea. We believe that this work provides a new direction for the development of big data </span>motion analysis and self-powered smart exercise devices.</span></span></p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138513567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New concept of two-cascade energy compression systems based on drift step recovery diodes","authors":"A.F. Kardo-Sysoev ,&nbsp;M.N. Cherenev ,&nbsp;A.G. Lyublinsky ,&nbsp;M.I. Vexler","doi":"10.1016/j.mee.2023.112126","DOIUrl":"10.1016/j.mee.2023.112126","url":null,"abstract":"<div><p><span>A new concept of effective high-voltage nanosecond </span>pulse generators<span> based on two compression cascades of drift step recovery diodes (DSRDs) is presented. The main advantage of the proposed approach arises from the decoupling of the operation cycles of DSRD cascades while using a single primary switch. This greatly improves the overall efficiency of the system. The first DSRD cascade operates with low pulse current densities. Its operation cycles can be extended resulting in an increase of the compression factor and pulse energy, whereas the loss level is kept at a minimum. The second DSRD cascade operates with high current densities, but the duration of its cycles can be chosen much shorter which ensures good efficiency too. Furthermore, an extension of the working cycle of the first DSRD cascade makes the requirement for the primary switch milder so that even relatively slow low-voltage switches can be employed.</span></p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138513560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}