Microelectronic Engineering最新文献

{"title":"Strategies for avoiding delamination in system-in-packaging devices","authors":"Andrei Alaferdov ,&nbsp;Ricardo T. Yoshioka ,&nbsp;Carolina C.P. Nunes ,&nbsp;Matheus Dias Sousa ,&nbsp;Valdeci Carvalho ,&nbsp;Igor Fernandes Namba ,&nbsp;Claudemir Coral","doi":"10.1016/j.mee.2023.112089","DOIUrl":"10.1016/j.mee.2023.112089","url":null,"abstract":"<div><p><span>Approaches such as the modification of substrate design and the use of different types of underfill/epoxy mold compound were proposed to solve the delamination problem in system-in-packaging devices (SiP). Energy dispersive spectroscopy, scanning electronic and acoustic microscopy were employed to evaluate the proposed changes in device structure. The effects of dispensing and curing temperature as well as of viscosity on the </span>underfill penetration ability under the component region were investigated. It was found that besides the excess of flux residue, the root cause of the delamination/expansion problem in SiP devices submitted to high temperatures is the presence of a large size of voids under the component. The use of a substrate design with cavity under the component region containing two entrances and the application of underfill was considered as a solution of the delamination problem. The reliability of this strategy was confirmed by a large sample size of fabricated devices.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47471523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Nano-capsuled thermal interface materials filler using defective multilayered graphene-coated silver nanoparticles","authors":"Sungjun Choi ,&nbsp;Dongho Shin ,&nbsp;Sarah EunKyung Kim ,&nbsp;Changsun Yun ,&nbsp;Yik Yee Tan ,&nbsp;Caroline Sunyong Lee","doi":"10.1016/j.mee.2023.112082","DOIUrl":"10.1016/j.mee.2023.112082","url":null,"abstract":"<div><p><span><span><span>To increase the thermal conductivity of thermal </span>interface materials<span> (TIM), the selection of thermally conductive filler is crucial. In this study, defective graphene-coated </span></span>silver nanoparticles<span> (Ag NPs) were selected as TIM fillers with low electrical resistivity. Poly-vinylpyrrolidone (PVP) coated Ag NPs were fabricated by polyol<span> process to be used as a precursor, while a multi-layer graphene (MLG) coated layer about 3–4 nm in thickness was formed on the surface of Ag NPs which is 95 nm through a chemical vapor deposition<span><span> (CVD) process. For application as a metal TIM filler for MLG-coated Ag NPs, the thermal properties of MLG-coated Ag NPs with varying ratios of PVP solution added to the PVP-coated Ag NPs during CVD, were evaluated. Moreover, the peak for crystalline carbon was confirmed through </span>XRD analysis at 26.207°, while the d-spacing was measured to be 3.40 Å. Through Raman analysis, the presence of D peak (1350 cm</span></span></span></span>⁻¹), G peak (1590 cm⁻¹), and 2D peak (2850 cm⁻¹) proved the successful formation of defective MLG on the surface of Ag NPs. Finally, high thermal conductivity of 71 W/(m∙K) with electrical resistivity of 6.0 × 10⁻⁸<span> Ω∙m was obtained when adding 60 wt% PVP solution to PVP-coated Ag NPs during CVD, showing complete isolation among MLG-coated Ag NPs while PVP solution added less than 60 wt% did not prevent Ag NPs from coarsening, increasing its electrical resistivity. Therefore, nano-capsuled TIM fillers composed of defective MLG-coated Ag NPs with high thermal conductivities were obtained to demonstrate their potential for high-performance computing devices in thermal management.</span></p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44060811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A simple figure of merit to identify the first layer to degrade and fail in dual layer SiOx/HfO2 gate dielectric stacks","authors":"Andrea Padovani ,&nbsp;Paolo La Torraca","doi":"10.1016/j.mee.2023.112080","DOIUrl":"10.1016/j.mee.2023.112080","url":null,"abstract":"<div><p>Understanding the degradation dynamics and the breakdown sequence of a bilayer high-k (HK) gate dielectric stack is crucial for the improvement of device reliability. We present a new Figure of Merit (FoM), the IL/HK Degradation Index, that depends on fundamental materials properties (the dielectric breakdown strength and the dielectric constant) and can be used to easily and quickly identify the first layer to degrade and fail in a bilayer SiO₂/HK dielectric stack. Its dependence on IL and HK material parameters is investigated and its validity is demonstrated by means of accurate physics-based simulations of the degradation process. The proposed FoM can be easily used to understand the degradation dynamics of the gate dielectric stack, providing critical insights for device reliability improvement.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45860395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability challenges in CMOS technology: A manufacturing process perspective","authors":"Qiao Teng ,&nbsp;Yongkang Hu ,&nbsp;Ran Cheng ,&nbsp;Yongyu Wu ,&nbsp;Guodong Zhou ,&nbsp;Dawei Gao","doi":"10.1016/j.mee.2023.112086","DOIUrl":"10.1016/j.mee.2023.112086","url":null,"abstract":"<div><p><span>With the development of automotive electronics, the characteristics of device reliability have received widespread attention. The improvement of device reliability primarily depends on the manufacturing process's quality. This work reviews the inherent relationship between </span>manufacturing processes and reliability with a detailed introduction to the components and failure indices of wafer-level reliability testing. Furthermore, it focuses on the complementary metal-oxide-semiconductor (CMOS) manufacturing process and how device reliability can be enhanced through optimization in front-end-of-line and back-end-of-line processes. Reliability serves as a crucial indicator of device quality, and further efforts are required to achieve higher reliability through process optimization.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43226766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel programming circuit for memristors","authors":"Shengtao Tu ,&nbsp;Jinyu Li ,&nbsp;Yanyun Ren ,&nbsp;Qin Jiang ,&nbsp;Shisheng Xiong","doi":"10.1016/j.mee.2023.112072","DOIUrl":"10.1016/j.mee.2023.112072","url":null,"abstract":"<div><p><span><span><span>Memristor has attracted a lot of interest due to its high processing speed, </span>low power consumption and high integration ability, which is critical for electronic systems and memory-centric computing. However, the memristor </span>programming circuit and strategy are still inflexible and complex, since the signal generator/collector and stimulate pulse must be carefully matched and designed based on memristor intrinsic characteristics without reconfigurable. Here, a simple and effective circuit only consists a parallel reference-resistor-and-NMOS is designed to program memristor with a &gt;99% memristance precision. And the amplitude and width of stimulate pulse are fixed to ±4 V and 5 ms, respectively. In order to cope with the device variation, such as ±10% tolerance of transition voltage, an optimized programming strategy was proposed and demonstrated great robustness. Additionally, a set of reference resistors and NMOSs have been added to facilitate multi-level memristance operation without requiring any changes to the circuit structure. This program circuit was also employed to program memristor crossbar remains 99% precision. In the end, a memristor-based </span>convolutional neural network which controlled by our optimized programming circuit was used for image recognition, and 89.36% accuracy can be achieved even under 15.8% memristance tolerance. This novel circuit demonstrates a simple and flexible strategy in memristor programming, providing a new way to control memristor crossbar for practical application.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45594179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electron beam lithography and dimensional metrology for fin and nanowire devices on Ge, SiGe and GeOI substrates","authors":"Nikolay Petkov ,&nbsp;Margarita Georgieva ,&nbsp;Sinan Bugu ,&nbsp;Ray Duffy ,&nbsp;Brendan McCarthy ,&nbsp;Maksym Myronov ,&nbsp;Ann-Marie Kelleher ,&nbsp;Graeme Maxwell ,&nbsp;Giorgos Fagas","doi":"10.1016/j.mee.2023.112071","DOIUrl":"10.1016/j.mee.2023.112071","url":null,"abstract":"<div><p>Until now there is no systematic study on the effect of the substrate type on the hydrogen silsesquioxane (HSQ) electron beam lithography (EBL) patterning process. We investigate arrays of line structures with varying width and spacing, starting at 10 nm, exposed at varying dose, and developed by salty NaOH and TMAH developers on group IV semiconductor substrates. We demonstrate that the HSQ EBL process on Ge is much more limited in achieving the smallest obtainable features, having optimal uniformity and fidelity, in comparison to Si. Monte-Carlo simulations of the e-beam/substrate interactions for “pure” Si and Ge substrates, and varying content Ge/Si epitaxial layers on Si, suggest that the limitations seen are directly linked to back-scattered electron (BSE) generation. As predicted by the simulations and shown experimentally, improved fidelity and resolution of the features can be achieved by minimizing the (BSE) generation coming from the Ge contribution in the substartes. Finally, from a metrology perspective, it is demonstrated that although line patterns may appear resolved in SEM images, the variation in the brightness across neighbouring lines is a key parameter in understanding the resist clearance between lines, that will affect the next etching step for pattern transfer onto the underlying substrate. These results are important for patterning high-density line structures and nano-device engineering as required for realising state-of-the art laterally stacked group IV multi-channel field effect transistors (FETs).</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41475901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fabrication of silicon nitride membrane nanoelectromechanical resonator","authors":"Hao Xu,&nbsp;Srisaran Venkatachalam,&nbsp;Christophe Boyaval,&nbsp;Pascal Tilmant,&nbsp;Francois Vaurette,&nbsp;Yves Deblock,&nbsp;Didier Theron,&nbsp;Xin Zhou","doi":"10.1016/j.mee.2023.112064","DOIUrl":"10.1016/j.mee.2023.112064","url":null,"abstract":"<div><p><span><span>In this work, we present details of the nanofabrication process<span><span> for achieving a silicon nitride nanoelectromechanical </span>resonator, consisting of a membrane covered with a thin </span></span>aluminium layer capacitively coupled to a suspended top gate. Critical nanofabrication steps have been discussed, including the </span><span><math><msub><mi>XeF</mi><mn>2</mn></msub></math></span><span> selective etching process to release the silicon nitride membrane from the substrate and the reflow process to fabricate a top gate of a suspended membrane. This ultra-clean and CMOS-compatible process allows the silicon nitride membrane to have a high quality factor (</span><span><math><mo>∼</mo></math></span>1.1<span><math><mo>×</mo><msup><mn>10</mn><mn>4</mn></msup></math></span><span>) at room temperature and offers access to electrical integration with external circuits with high efficiency. In addition, we also demonstrate parametric amplification and de-amplification of the input signals by exploiting this suspended top gate. The measurement results of phase-sensitive amplifications have also been well fit by analytical caculations. The present work provides essential building blocks for further exploration of silicon nitride membrane based nanoelectromechanical resonators that can be efficiently integrated into large-scale electrical circuits.</span></p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42100900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Parameter analysis and electrochemical properties of 4,6-Dimethyl-2-mercaptopyrimidine for mitigating Cu prominence in through silicon vias filling","authors":"Fuliang Wang ,&nbsp;Xi He ,&nbsp;Bo Wu ,&nbsp;Qingyu Li ,&nbsp;Qibin Niu ,&nbsp;Kai Niu ,&nbsp;Wenhao Yao","doi":"10.1016/j.mee.2023.112056","DOIUrl":"10.1016/j.mee.2023.112056","url":null,"abstract":"<div><p>Through silicon<span><span> via (TSV) is the core technology that implements three-dimensional (3D) integrated packaging in integrated circuits. Electrodeposition<span> defects affect the reliability of TSVs. In particular, the surface Cu protrusions can lead to structural deformations, which significantly affect the reliability of TSVs. In this study, 4,6-Dimethyl-2-mercaptopyrimidine (DMP) is studied as a leveller additive for TSV electroplating, along with the effect of the </span></span>deposition parameters<span><span> on the TSV filling process and surface morphology. To evaluate the filling performance of DMP, linear sweep </span>voltammetry (LSV) is performed to investigate how the additives affect the filling mechanism. Finally, the conditions of this levelling agent in TSV plating are predicted based on LSV curves and validated using plating experiments.</span></span></p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47021297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultra-low power logic in memory with commercial grade memristors and FPGA-based smart-IMPLY architecture","authors":"Lorenzo Benatti,&nbsp;Tommaso Zanotti,&nbsp;Paolo Pavan,&nbsp;Francesco Maria Puglisi","doi":"10.1016/j.mee.2023.112062","DOIUrl":"10.1016/j.mee.2023.112062","url":null,"abstract":"<div><p>Reducing power consumption in nowadays computer technologies represents an increasingly difficult challenge. Conventional computing architectures suffer from the so-called von Neumann bottleneck (VNB), which consists in the continuous need to exchange data and instructions between the memory and the processing unit, leading to significant and apparently unavoidable power consumption. Even the hardware typically employed to run Artificial Intelligence (AI) algorithms, such as Deep Neural Networks (DNN), suffers from this limitation. A change of paradigm is so needed to comply with the ever-increasing demand for ultra-low power, autonomous, and intelligent systems. From this perspective, emerging memristive non-volatile memories are considered a good candidate to lead this technological transition toward the next-generation hardware platforms, enabling the possibility to store and process information in the same place, therefore bypassing the VNB. To evaluate the state of current public-available devices, in this work commercial-grade packaged Self Directed Channel memristors are thoroughly studied to evaluate their performance in the framework of in-memory computing. Specifically, the operating conditions allowing both analog update of the synaptic weight and stable binary switching are identified, along with the associated issues. To this purpose, a dedicated yet prototypical system based on an FPGA control platform is designed and realized. Then, it is exploited to fully characterize the performance in terms of power consumption of an innovative Smart IMPLY (SIMPLY) Logic-in-Memory (LiM) computing framework that allows reliable in-memory computation of classical Boolean operations. The projection of these results to the nanoseconds regime leads to an estimation of the real potential of this computing paradigm. Although not investigated in this work, the presented platform can also be exploited to test memristor-based SNN and Binarized DNNs (i.e., BNN), that can be combined with LiM to provide the heterogeneous flexible architecture envisioned as the long-term goal for ubiquitous and pervasive <strong>AI.</strong></p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48446686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fabrication of curved MLA-grating based on 3D printing mold and vacuum-assisted deformation replication process","authors":"Jian Jin ,&nbsp;Jun Wu ,&nbsp;Zhenhua Yu ,&nbsp;Zhong Wang ,&nbsp;Xudi Wang","doi":"10.1016/j.mee.2023.112059","DOIUrl":"10.1016/j.mee.2023.112059","url":null,"abstract":"<div><p><span><span>The combination of Microlens Array (MLA) with a grating structure is an effective means of improving light shaping efficiency due to the light dispersion effects of both elements. This paper proposes an innovative method for fabricating a curved MLA-grating composite element using a </span>3D printing mold and vacuum-assisted deformation replication process. In addition to the cost advantages of the process, the </span>optical parameters<span><span><span> such as type and line-density of grating, curvature and aperture size of the microlens can be effectively controlled, so as to bring different diffraction and focusing effects. Test results demonstrate that the curved MLA-grating element has superior light dispersion efficiency, making it useful in improving the illumination range of light sources. Additionally, due to the focusing effect of the curved substrate, this element holds promise for enhancing the </span>light energy utilization rate in the </span>photovoltaic field.</span></p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2023-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44884093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}