Microelectronic Engineering最新文献

{"title":"TCAD simulations of radiation damage in 4H-SiC","authors":"Jürgen Burin,&nbsp;Christopher Hahn,&nbsp;Philipp Gaggl,&nbsp;Andreas Gsponer,&nbsp;Simon Waid,&nbsp;Thomas Bergauer","doi":"10.1016/j.mee.2025.112352","DOIUrl":"10.1016/j.mee.2025.112352","url":null,"abstract":"<div><div>In this paper we present simulation based radiation damage modeling of 4H silicon carbide (SiC) using the technology computer aided design (TCAD) tools for up to 1 kV forward and backward bias. After verifying the TCAD framework from Global TCAD Solutions (GTS) against Sentaurus simulations for silicon we use it to approximate measurements of neutron-irradiated 4H-SiC particle detectors, i.e., pin-diodes. Based on our simulations we are not only able to evaluate the accuracy of the predictions but also to provide an explanation for the almost negligible current of radiated devices under high forward bias.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112352"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143894894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Theoretical insights into the impact of border and interface traps on hysteresis in monolayer MoS2 FETs","authors":"Rittik Ghosh,&nbsp;Alexandros Provias,&nbsp;Alexander Karl,&nbsp;Christoph Wilhelmer,&nbsp;Theresia Knobloch,&nbsp;Mohammad Rasool Davoudi,&nbsp;Seyed Mehdi Sattari-Esfahlan,&nbsp;Dominic Waldhör,&nbsp;Tibor Grasser","doi":"10.1016/j.mee.2025.112333","DOIUrl":"10.1016/j.mee.2025.112333","url":null,"abstract":"<div><div>Threshold voltage hysteresis <span><math><mfenced><mrow><mi>Δ</mi><msub><mi>V</mi><mi>h</mi></msub></mrow></mfenced></math></span> in two-dimensional transistor transfer characteristics poses a bottleneck in achieving stable 2D CMOS integrated circuits. Hysteresis is primarily attributed to traps at the channel/oxide interface as well as in the oxide. In this study, we present a physics-based self-consistent modeling framework to investigate the impact of border and interface traps on <span><math><mi>Δ</mi><msub><mi>V</mi><mi>h</mi></msub></math></span> and apply it to monolayer (1-L) MoS₂ field-effect transistors (FETs). The transient trapping and detrapping of charges during gate voltage sweeps across a wide range of frequencies and temperatures is analyzed using a two-state non-radiative multi-phonon (NMP) model. Our results reveal distinct dynamic responses for slow border and fast interface traps, with border traps exhibiting slower time constants due to larger relaxation energies and interface traps showing fast nuclear tunneling-dominated dynamics resulting from the smaller relaxation energies. These simulations highlights the critical role of the spatial and energetic distributions of the traps in determining <span><math><mi>Δ</mi><msub><mi>V</mi><mi>h</mi></msub></math></span>, providing insights into the stability of 2D FETs and paving the way for improved device engineering.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112333"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143609663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fabrication of industrial grade GMR multilayer magnetic sensors for non-recording applications","authors":"Bhagaban Behera,&nbsp;Umesh P. Borole,&nbsp;Jakeer Khan,&nbsp;Harish C. Barshilia,&nbsp;P. Chowdhury","doi":"10.1016/j.mee.2024.112311","DOIUrl":"10.1016/j.mee.2024.112311","url":null,"abstract":"<div><div>Giant Magnetoresistance (GMR) technology is now becoming a popular choice in the industrial market for non-recording applications (sensor applications). In these applications, the sensor's characteristics need to be engineered for high linearity, reversibility, and high thermal stability. Among two different types of GMR technologies, such as GMR-multilayer (GMR-ML) and GMR- spin valves (GMR-SV), an attempt was made to fabricate a sensing element with high throughput based on GMR-ML due to its cost-effectiveness and relatively higher dynamic field range. Further, sensor was used as linear sensor in both omni-polar (i.e. by default) as well as bipolar (i.e. biased with permanent magnet for converting omfig ni-polar characteristics to bipolar characteristics). A detailed pilot scale fabrication of a GMR sensor with a yield of 88 % on a 4-in. wafer was presented. All the products developed using GMR-ML were evaluated in the real-time applications environment.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112311"},"PeriodicalIF":2.6,"publicationDate":"2025-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Unraveling the role of post-annealing in IGZO transistor for memory applications","authors":"Nayeon Kim ,&nbsp;Jiae Jeong ,&nbsp;Jae Woo Lee ,&nbsp;Jiyong Woo","doi":"10.1016/j.mee.2025.112322","DOIUrl":"10.1016/j.mee.2025.112322","url":null,"abstract":"<div><div>We demonstrate that post-annealing techniques are important for achieving the transfer characteristics of indium‑gallium‑zinc oxide (IGZO) transistors and identify that their role depends on the sputter-deposited IGZO film conditions. The as-fabricated transistor with a thin IGZO channel, HfO₂ gate dielectric, and Mo gate electrode exhibits a constant drain current (I_DS) over gate voltage (V_GS). Although the oxygen (O₂) plasma gas rate is adjusted from 0.2 to 1 sccm with an argon gas rate of 30 sccm during IGZO deposition, the I_DS level was reduced by a factor of 10⁴. Notably, V_GS-controlled transfer behavior of the transistors only starts after post-annealing is performed at temperatures above 300 °C, regardless of which IGZO channel properties are used. More specifically, since oxygen vacancies (V_Os) serve as carriers in the IGZO, annealing in different O₂ gas or air environments to generate or reduce the number of V_Os is found to be optimal for the V_O-rich or V_O-poor channels, respectively. In this study, we reveal that oxidation annealing appears to be a more effective way for achieving improved gate controllability (e.g., subthreshold swing). Accordingly, we further analyze how the V_Os in the IGZO are involved in switching by examining the effect of annealing temperature and gate dielectric materials on the transfer curve. These results indicate that V_Os in the bulk need to be annihilated to lower the off-state I_DS, while a sufficient number of V_Os near the channel and gate dielectric interface should be ensured to responded by V_GS for rapid switching.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112322"},"PeriodicalIF":2.6,"publicationDate":"2025-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of edge bead removal (EBR) process to enhance defect reduction in optical lithography","authors":"Bishnu P. Khanal,&nbsp;Marlene Dugger","doi":"10.1016/j.mee.2025.112330","DOIUrl":"10.1016/j.mee.2025.112330","url":null,"abstract":"<div><div>Defect reduction remains a critical objective in the integrated circuit manufacturing process, particularly within the highly re-entrant lithography modules where minimizing defects is crucial. Defects at the wafer edge can contaminate lithography modules and downstream processing equipment, leading to redistribution onto the wafer surface and adversely affecting overall device yield. A persistent challenge in the resist coating process is the formation of resist edge beads, driven by the strong Van der Waals attraction of excess photoresist (PR) to itself and the underlying substrate. The edge bead removal (EBR) process is a standard cleaning step designed to eliminate these edge beads and prevent potential contamination.</div><div>In this study, we identify the sources of EBR induced defects and additional EBR process encroachment toward edge patterning during the EBR cleaning process. This study provides a comprehensive study aimed at optimizing the EBR cleaning process to effectively eliminate EBR-induced defects, thereby enhancing overall device yield. Specifically, we identify three primary defects induced by the EBR cleaning process: rainbow-type, finger-shaped, and teardrop-type defects. Our experimental study reveals that in addition to EBR rinse time, PR cast time is crucial parameters contributing to the formation of these defects. By properly optimizing the PR cast time and EBR rinse time, we were able to remove nearly 100 % of dense clusters of defects that were easily visible even at low magnification optical microscopy throughout the wafer edge. We observed that shorter PR casting times shows edge defects caused by inefficient EBR process because of insufficient time for PR to fully settle causing superfluous PR to continue flowing toward wafer edge during EBR clearing step, leading to partial removal of PR at the wafer edge and the formation of rainbow defects. Proper optimization of both PR casting time and EBR chemistries dispense time is essential to resolve these defects, ensuring efficient EBR cleaning process and improved overall device yield.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112330"},"PeriodicalIF":2.6,"publicationDate":"2025-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143444796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimized fabrication of subwavelength slanted gratings via laser interference lithography and faraday cage-assisted etching","authors":"Zhiyuan Jiang,&nbsp;Xingzhi Zhang,&nbsp;Wei He,&nbsp;Kai Jiang,&nbsp;Liang Wang","doi":"10.1016/j.mee.2025.112323","DOIUrl":"10.1016/j.mee.2025.112323","url":null,"abstract":"<div><div>Subwavelength slanted gratings are crucial components in devices such as augmented reality systems and optoelectronic sensors due to their high diffraction efficiency and compact design. However, their fabrication is often hindered by high costs and limited structural control. This paper presents a novel fabrication method that combines a laser interference lithography (LIL) process, optimized using a two-dimensional lithography simulation model, with a Faraday cage-assisted reactive ion etching (RIE) process. The simulation model integrates exposure intensity analysis under the standing wave effect with photoresist contrast curve characteristics, enabling accurate simulation of photoresist patterns and providing precise feedback on exposure time and the angle between exposure light beams to achieve precise control of key parameters, such as period and duty cycle. Compared to traditional models, it reduces complexity while delivering high accuracy. The LIL process optimized by this model achieves negligible period error and a duty cycle error <span><math><mo>≤</mo><mn>0.01</mn></math></span>. Faraday cage-assisted RIE further enhances control over grating height and tilt angle, achieving near-zero deviations. This scalable and cost-effective method provides a reliable solution for fabricating high-precision subwavelength slanted gratings, advancing their practical applications in sophisticated optical systems.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112323"},"PeriodicalIF":2.6,"publicationDate":"2025-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal management of through-silicon vias and back-end-of-line layers in 3D ICs: A comprehensive review","authors":"Hongbang Zhang ,&nbsp;Miao Tian ,&nbsp;Xiaokun Gu","doi":"10.1016/j.mee.2025.112325","DOIUrl":"10.1016/j.mee.2025.112325","url":null,"abstract":"<div><div>Three-dimensional integrated circuits (3D ICs) have emerged at the forefront of semiconductor research due to their potential for enhancing performance and reducing power consumption. As semiconductor technology advances, the continuous miniaturization and increasing integration density of 3D ICs have made size and interface effects more pronounced, leading to higher heat flux densities and more complex thermal management challenges. Through‑silicon via (TSV) and back-end-of-line (BEOL) structures, as core components of 3D ICs, are responsible for horizontal and vertical interconnections and directly affect the thermal transport performance within the chip. In this review, we provide an overview of the current state of thermal management in TSVs and BEOL structures, discussing heat dissipation performance, thermal parameter extraction, structural optimization, and the development of layout algorithms. In response to the challenges of cross-scale simulations and the difficulty of characterizing the thermal properties and temperature distribution of complex micro-nano scale structures, the current state of theoretical calculations and thermal testing techniques at the micro-nano scale, which have been evolved as powerful tools in thermal management of 3D ICs, is also presented. This review summarizes the key advances and challenges in this field, highlighting the importance of addressing these issues to optimize TSVs and BEOL designs and enhance the thermal management performance of 3D ICs, providing valuable reference and guidance for future research.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112325"},"PeriodicalIF":2.6,"publicationDate":"2025-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143474091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Amorphous indium gallium zinc oxide thin film transistors (a-IGZO-TFTs): Exciting prospects and fabrication challenges","authors":"J. Ajayan ,&nbsp;S. Sreejith ,&nbsp;N. Aruna Kumari ,&nbsp;M. Manikandan ,&nbsp;Sachidananda Sen ,&nbsp;Maneesh Kumar","doi":"10.1016/j.mee.2025.112327","DOIUrl":"10.1016/j.mee.2025.112327","url":null,"abstract":"<div><div>In today's consumer electronics market, major manufacturing companies may be profitable and scalable thanks to technologies like thin-film transistors (TFTs). TFTs are found in TVs, smartphones, laptops, brain-like synaptic transistors, back-planes in CMOS image sensors, integrated circuits (ICs), flexible &amp; wearable electronics, power switching circuits, back-end-of-line (BEOL) transistor elements in 3D-logic and cell transistors in dynamic random-access memory (DRAM). They have also been proposed as a potential solution for flexible CPUs. A high mobility of 74.4 cm²/Vs and I_ON/I_OFF of 3.39 × 10⁹ and a V_ON of less than ±0.1 V and a SS of less than 0.1 V/dec were achieved in a-IGZO based TFTs. Numerous efforts have been made to enhance the a-IGZO TFTs' electrical characteristics by optimizing the fabrication process. Numerous studies have also addressed the instability problems, such as the a-IGZO devices' hot-carrier effects, self-heating, and charge-trapping. TFTs with a-IGZO are being extensively studied adopting the a vertical-channel approach in order to be used in 3-D electronic devices. This article reviews the recent developments in materials and architectures, performance overview of IGZO-TFTs, advances and challenges in fabrication technologies and reliability issues &amp; degradation mechanisms of IGZO-TFTs.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112327"},"PeriodicalIF":2.6,"publicationDate":"2025-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143372220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Spin coating in semiconductor lithography: Advances in modeling and future prospects","authors":"Pan Liu ,&nbsp;Liejie Huang ,&nbsp;Chaoyi Zheng ,&nbsp;Yanan Bao ,&nbsp;Dawei Gao ,&nbsp;Guodong Zhou","doi":"10.1016/j.mee.2025.112326","DOIUrl":"10.1016/j.mee.2025.112326","url":null,"abstract":"<div><div>With the development of advanced integrated circuit technologies, semiconductor manufacturing processes have become increasingly important. Photolithography is one of the most critical and costly steps in chip manufacturing, and the quality of the photoresist film formed during the subprocess of spin-coating significantly impacts photolithography performance. The thickness of photoresist films ranges from several hundred nanometers to tens of micrometers, with uniformity requirements typically within ±1 %. These stringent specifications pose significant challenges to the stability and precision of the spin coating process. This review outlines the research progress on spin-coating and discusses various model-building methods, including theoretical analysis, experimentation, simulation, and machine learning. The paper highlights new experimental approaches and recent advancements aimed at optimizing the spin-coating process under different conditions.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112326"},"PeriodicalIF":2.6,"publicationDate":"2025-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143314795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of constant bias stress on reliability of IGZO thin-film transistors on softening polymer","authors":"Gerardo Gutierrez-Heredia ,&nbsp;Ovidio Rodriguez-Lopez ,&nbsp;Pedro Emanuel Rocha-Flores ,&nbsp;Walter E. Voit","doi":"10.1016/j.mee.2025.112331","DOIUrl":"10.1016/j.mee.2025.112331","url":null,"abstract":"<div><div>This study analyzed the electrical behavior of indium‑gallium‑zinc-oxide (IGZO) thin-film transistors (TFTs) under different applied voltages. The IGZO TFTs were fabricated on a polymer substrate using full photolithographic processes. The electrical performance was monitored under constant bias stress for 10,000 s and the analysis revealed relatively high field-effect mobility (&gt;10 cm²/Vs) when higher voltages (&gt;5 V) were applied to the IGZO TFTs. Furthermore, the experimental results demonstrated shifts in the threshold voltage (V_TH), mobility, and saturation drain current, exhibiting a strong dependence on the applied voltage. After 10,000 s of bias stress, the threshold voltage shift varied by 0.5 V for the lowest applied voltage and exceeded 5 V for the higher values. Moreover, the electrical analysis indicated a significant reduction in the lifetime of IGZO TFTs when the applied voltage exceeded 15 V. These findings enable a comparative analysis of the impact of bias stress on mobility, V_TH, and driving current, offering a pathway to optimize the electrical performance of TFTs-based flexible applications. Furthermore, by exploring the mechanism behind the changes induced by the constant electric field at the gate contact, this work provides insights for predicting the reliability and lifetime of novel devices tailored for wearable, flexible, and biomedical technologies.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112331"},"PeriodicalIF":2.6,"publicationDate":"2025-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}