{"title":"The electronic and optical properties of the monolayer Mo(SxSe1-x)2 by the first-principle calculations","authors":"Chuan-Zhen Zhao, Tai-Ning Xu, Hui-Jing Hu","doi":"10.1016/j.mee.2025.112349","DOIUrl":"10.1016/j.mee.2025.112349","url":null,"abstract":"<div><div>First-principles calculations are conducted to explore the electronic and optical properties of the monolayer Mo(S<sub>x</sub>Se<sub>1-x</sub>)<sub>2</sub>. It is found that the monolayer Mo(S<sub>x</sub>Se<sub>1-x</sub>)<sub>2</sub> possesses a direct bandgap. Through fitting the theoretical and experimental data, the bandgap bowing parameter of 0.051 eV is attained. The enlargement of the bandgap energy is by reason of the decline of the K VBM. In the full component range, the downward movements of the K CBM and the K VBM are dominated by the <span><math><msub><mi>p</mi><mrow><mi>S</mi><mo>−</mo><mn>3</mn><mi>p</mi></mrow></msub><mo>−</mo><msub><mi>d</mi><mrow><mi>Mo</mi><mo>−</mo><mn>4</mn><mi>d</mi></mrow></msub></math></span> coupling interaction and the total p-d coupling interaction, respectively. For the optical properties, it is found that increasing S component can reduce the static dielectric constant. However, the B and C excitons as well as E<sub>3</sub> shift toward the higher energy direction with increasing S component. It is also found that increasing S component has a small effect on enhancing the light absorption. The photoconductivity shows a similar result with the absorptivity.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112349"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143777216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Siyuan Wang , Ming Dong , Jiang He , Guancheng Wu , Xiang Li , Xiaojun Pan , Jiansheng Wu , Rongrong Bao , Caofeng Pan
{"title":"A multi-user wearable waistband system for real-time health monitoring of respiration, ECG, and body temperature","authors":"Siyuan Wang , Ming Dong , Jiang He , Guancheng Wu , Xiang Li , Xiaojun Pan , Jiansheng Wu , Rongrong Bao , Caofeng Pan","doi":"10.1016/j.mee.2025.112346","DOIUrl":"10.1016/j.mee.2025.112346","url":null,"abstract":"<div><div>Wearable health monitoring systems have gained significant attention for real-time physiological signal tracking, particularly in elderly care settings where continuous, non-invasive monitoring is critical. Current systems, however, face limitations in multi-signal integration, user comfort, and practicality for long-term use. Existing approaches often rely on separate devices for measuring vital signs, leading to cumbersome setups and restricted mobility. Additionally, few solutions support simultaneous multi-user monitoring, hindering scalability in group care environments like nursing homes. In this study, we present a highly integrated waistband device that addresses these gaps by concurrently measuring respiration, electrocardiogram (ECG), and body temperature. The respiratory sensor employs a resistive pressure sensor. Its alignment with the ECG electrodes and the temperature sensor eliminates the need for auxiliary respiratory devices (e.g., masks) and enhances wearability. With the integration of a Bluetooth transmission circuit system, this real-time health monitoring system enables long-term stable testing for multiple users. A 24-h synchronized test involving 10 participants was conducted, demonstrating effective health monitoring capabilities and the potential to identify underlying health issues. This innovation provides a scalable, comfortable solution for intelligent healthcare systems, demonstrating practical value in elderly care applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112346"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143784069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Finite element modeling analysis of misalignment impact on simulated electrical RC in scaling hybrid bonding pairs","authors":"Guoqiang Zhao , Yi Zhao","doi":"10.1016/j.mee.2025.112347","DOIUrl":"10.1016/j.mee.2025.112347","url":null,"abstract":"<div><div>During the scaling down of hybrid bonding pairs, controllable misalignment is particularly important for ensuring remarkable electrical performance. This article presents the finite element modeling methodology to preview the significance of misalignment on resistance and capacitance values. Design parameters such as the via array, pad size, shape, and asymmetric structure are comprehensively considered. The results show that the electrical properties of interconnects at the small pitch is more sensitive to misalignment. The via array affects the current distribution serving as the inter-metal connection channel. The size and shape of the pad directly determine the effective contact area and effective space under various misalignment. The alignment error redundancy provided by the asymmetric structure is an option to alleviate the problem. This work contributes to understanding the impact weight of misalignment on electrical performance under different design conditions and formulating appropriate alignment rules.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112347"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143903722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Murugapandiyan , A.S. Augustine Fletcher , Md. Tanvir Hasan , N. Ramkumar , A. Revathy
{"title":"Recent advancement in β-Ga2O3 MOSFETs: From material growth to device architectures for high-power electronics","authors":"P. Murugapandiyan , A.S. Augustine Fletcher , Md. Tanvir Hasan , N. Ramkumar , A. Revathy","doi":"10.1016/j.mee.2025.112359","DOIUrl":"10.1016/j.mee.2025.112359","url":null,"abstract":"<div><div>Beta‑gallium oxide (β-Ga<sub>2</sub>O<sub>3</sub>) has emerged as a promising semiconductor material for next-generation power electronics due to its ultra-wide bandgap (4.9 eV), exceptional breakdown electric field (8 MV/cm), and compatibility with cost-effective melt growth methods for producing large-area single crystals. This comprehensive review examines recent advances in β-Ga<sub>2</sub>O<sub>3</sub> metal-oxide-semiconductor field-effect transistors (MOSFETs), spanning from material synthesis to device implementation. The review then investigates device architectures, examining both depletion-mode and enhancement-mode β-Ga<sub>2</sub>O<sub>3</sub> MOSFETs. We highlight crucial design elements including field plates, innovative gate structures, and channel engineering techniques that have enabled devices with breakdown voltages exceeding 2.3 kV and power figures of merit surpassing 150 MW/cm<sup>2</sup>. Additionally, we address significant challenges, particularly thermal management issues stemming from β-Ga<sub>2</sub>O<sub>3</sub>'s relatively low thermal conductivity (10–20 W/m·K) and the current absence of p-type doping capability, discussing various proposed solutions including diamond heat spreaders, heterogeneous substrate integration, and advanced packaging approaches. Finally, we examine emerging concepts such as nanomembrane transistors, fin structures, and heterojunction FETs, concluding with insights on future research directions for this promising semiconductor technology.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112359"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144071119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Anhan Liu , Shijun Yu , Shingo Nakamura , Akinari Sugiyama , Takashi Nishikawa , Dongwei Xu , Xiao Jin , Daixuan Wu , He Tian
{"title":"The role of etching gas purity in C4F8/Ar plasma to optimize SiO2 etching process","authors":"Anhan Liu , Shijun Yu , Shingo Nakamura , Akinari Sugiyama , Takashi Nishikawa , Dongwei Xu , Xiao Jin , Daixuan Wu , He Tian","doi":"10.1016/j.mee.2025.112353","DOIUrl":"10.1016/j.mee.2025.112353","url":null,"abstract":"<div><div>The relentless miniaturization of critical feature sizes in integrated circuits has set increasingly stringent demands on the precision of via etching processes. Current research predominantly focuses on the development of gases and optimization of processes. However, the role of etching gas purity and the impact of gas impurities have not yet been the subject of dedicated studies. Here, the etching behavior of silicon dioxide using two different purities of etching gases is investigated, examining the etching rate and morphology of SiO<sub>2</sub> films under identical etching parameters. Compared to 99.999 % purity, the 99.99999 % purity C<sub>4</sub>F<sub>8</sub> gas achieves a more stable and uniform etching rate with sidewall angles of 86.6° (closer to a 90° angle). This is primarily attributed to the reduction of etch-active impurities in the C<sub>4</sub>F<sub>8</sub> gas, which decreases etching variability and minimizes damage to the sidewall fluorocarbon protective layer. Our research provides theoretical and experimental support for the advancement of subsequent etching simulation studies and the application of high-purity etching gases.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112353"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143899199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Study on different failure mechanisms of MOSFET caused by different oxide defects in 14 nm FinFET IC","authors":"Yanfen Wang, Shijun Zheng, Shan Zhang, Junsheng Wang, Guang Lu, Gaojie Wen","doi":"10.1016/j.mee.2025.112350","DOIUrl":"10.1016/j.mee.2025.112350","url":null,"abstract":"<div><div>With the advent of FinFET technology, especially in the application of 14 nm and above nodes, the front-end-of-line (FEOL) defects at the transistor level have become increasingly significant. These minute FEOL defects have a critical impact on the yield and reliability of the ultimate chipset. This paper focuses on two types of FEOL defects identified in 14 nm FinFET technology. The research shows that both of these FEOL defects can lead to leakage in MOSFETs. We have conducted an in-depth analysis of the distinct failure mechanisms of these two defects and their potential formation causes. It is expected to help wafer factories achieve effective improvements. The study indicates that these two failure modes might be triggered by oxide defects in different steps of the FEOL process flow. Specifically, in one case, dielectric breakdown-induced epitaxy (DBIE) causes NMOS gate leakage, which might be ascribed to the presence of defects in the bottom interface layer (BIL) of the oxide. In another instance, PMOS leakage caused by germanium bridge defects might result from oxide defects as the etch stop layer (ESL) and the influence of subsequent process steps on the defects. This research provides an essential guiding direction for wafer factories to optimize the manufacturing process of 14 nm FinFET products and improve yield and quality. At the same time, this study also offers a valuable reference basis for the failure analysis of FinFET devices.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112350"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143927984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Biaohong Huang , Yuxuan Jiang , Jingyan Liu , Yizhuo Li , Qianhe Jin , Qishuai Huang , Tula R. Paudel , Tom Wu , Zhidong Zhang , Weijin Hu
{"title":"Enhancing ferroelectric resistive switching via polar order engineering in Sm-doped BiFeO3 films","authors":"Biaohong Huang , Yuxuan Jiang , Jingyan Liu , Yizhuo Li , Qianhe Jin , Qishuai Huang , Tula R. Paudel , Tom Wu , Zhidong Zhang , Weijin Hu","doi":"10.1016/j.mee.2025.112343","DOIUrl":"10.1016/j.mee.2025.112343","url":null,"abstract":"<div><div>Ferroelectric materials are promising for nonvolatile resistive memories due to their unique switchable diode effect. To improve the resistive switching performance, the fundamental correlation between the diode effect and the polar ordering should be unraveled. Here by the A-site substitution with Sm, we report the resistive switching in ferroelectric SrRuO<sub>3</sub>/Sm<sub><em>x</em></sub>Bi<sub>1-<em>x</em></sub>FeO<sub>3</sub> (<em>x</em> = 0, 0.1, 0.2)/Pt thin-film capacitors. We find that the ground state of BiFeO<sub>3</sub> changes from ferroelectric to antiferroelectric with increasing Sm substitution, which is accompanied by the fading of the resistive switching in Sm<sub>0.2</sub>Bi<sub>0.8</sub>FeO<sub>3</sub>, illustrating the decisive role of polarization in resistive switching. Moreover, similar dynamics between polarization and resistance states supports the close link between the ferroelectric domain growth and the resistive switching. Our SrRuO<sub>3</sub>/Sm<sub>0.1</sub>Bi<sub>0.9</sub>FeO<sub>3</sub>/Pt device achieved a high on/off ratio of 10<sup>4</sup> and fast switching speed of 6.25 ns, thanks to reduced leakage current from Sm doping while preserving ferroelectric properties. Our results thus provide a new approach to enhance the resistive memory performance of ferroelectric materials.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112343"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143681859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yunfei Shi , Songyi Jiang , Hong Yang , Yongkui Zhang , Longda Zhou , Zhigang Ji , Qianqian Liu , Qi Wang , Huilong Zhu , Jun Luo , Wenwu Wang
{"title":"Improved positive bias temperature instability of n-type vertical C-shaped-channel nanosheet FET by forming gas annealing","authors":"Yunfei Shi , Songyi Jiang , Hong Yang , Yongkui Zhang , Longda Zhou , Zhigang Ji , Qianqian Liu , Qi Wang , Huilong Zhu , Jun Luo , Wenwu Wang","doi":"10.1016/j.mee.2025.112357","DOIUrl":"10.1016/j.mee.2025.112357","url":null,"abstract":"<div><div>In this article, the influence of Forming Gas Annealing (FGA) on the Positive Bias Temperature Instability (PBTI) characteristics of n-vertical C-shaped-channel nanosheet FET (n-VCNFET) is studied. The experimental results show that the extra FGA can significantly suppress both the initial and generated interface traps in PBTI. Moreover, in ultra-fast PBTI the pre-existing trap and total trap of VCNFET due to FGA decreases by 35 % and 31 %, respectively. The energy level of the oxide trap under PBTI and recovery doesn't change, in other words, the FGA induces the oxide trap density of the devices to decrease by 36 % at 125 °C and 1.4 V V<sub>OV</sub>. The optimization effect of FGA annealing has been further confirmed from the perspective of trap generation. It provides a guideline for the PBTI improvement of VCNFET in trap scopes.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112357"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144068285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"AlGaN/GaN High electron Mobility Transistor (HEMT) based radio frequency power amplifiers for future wireless communication transmitters: Exciting prospects and challenges","authors":"J. Ajayan , S. Sreejith","doi":"10.1016/j.mee.2025.112342","DOIUrl":"10.1016/j.mee.2025.112342","url":null,"abstract":"<div><div>The power amplifiers (PAs) are indispensable for maintaining that both space and terrestrial transmitters fulfill the rigorous requirements for power consumption and, consequently, efficiency. Since solid-state PAs based on GaN HEMTs may offer the efficiency and power density performance to make them a feasible choice for space-borne active antennas, their availability is what propels integration for the satellite transmitters. Gain, output power (P<sub>out</sub>), bandwidth (BW), drain efficiency (DE), chip area, peak-to-average-power ratio (PAPR) and power added efficiency (PAE) are the key metrics usually used for measuring the performance of PAs. This article deals with the exciting prospects and challenges in the design and manufacturing of GaN-HEMT based RF-PAs. Doherty PAs are most popular among various PA architectures and they have recorded a maximum gain of over 30 dB, PAPR of over 11.5, PAE of over 81 % and an operating frequency of over 29 GHz. Other GaN HEMT based PAs have been reported a maximum operating frequency of over 192 GHz (using 100 nm GaN HEMT), gain of over 35 dB, and a P<sub>out</sub> of over 282 W. This article also highlights the various techniques for enhancing the broadband operation of GaN HEMT based PAs.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112342"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143593026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Comprehensive analysis and investigation of GaN LNA for 3–4 GHz using different gate-drain spacing","authors":"Md Hasnain Ansari , Siddharth Thakur , Neha Bajpai , Paramita Maity , Avinash Lahgere , Sheikh Aamir Ahsan , Manish Shah , Yogesh Singh Chauhan","doi":"10.1016/j.mee.2025.112361","DOIUrl":"10.1016/j.mee.2025.112361","url":null,"abstract":"<div><div>This work investigates the impact of the device technological parameter - gate-drain access region spacing (<span><math><msub><mi>L</mi><mi>GD</mi></msub></math></span>) - for GaN High Electron Mobility Transistors (HEMTs), on the design of low noise amplifiers (LNAs) for the 3–4 GHz range. We compare two GaN LNA variants, characterized by <span><math><msub><mi>L</mi><mi>GD</mi></msub></math></span> values of <span><math><mn>0.875</mn><mspace></mspace><mi>μ</mi><mi>m</mi></math></span> and <span><math><mn>1</mn><mspace></mspace><mi>μ</mi><mi>m</mi></math></span>, to highlight the significance of gate-drain spacings in determining performance metrics. This study contributes insights into the effect of gate-drain spacing on the GaN LNAs, and evaluates the RF characteristics, Noise Fig. (NF), and power metrics for different <span><math><msub><mi>L</mi><mi>GD</mi></msub></math></span> values. Based on our findings, we assert that the <span><math><mn>0.875</mn><mspace></mspace><mi>μ</mi><mi>m</mi><mspace></mspace><msub><mi>L</mi><mi>GD</mi></msub></math></span> LNA exhibits superior performance over its counterpart in the evaluated benchmarks, along with the physical reasoning.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112361"},"PeriodicalIF":2.6,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144134427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}