Microelectronic Engineering最新文献

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Dynamics of set and reset processes in HfO2 -based bipolar resistive switching devices 基于 HfO2 的双极电阻开关器件中的设定和复位过程的动态变化
IF 2.6 4区 工程技术
Microelectronic Engineering Pub Date : 2024-10-28 DOI: 10.1016/j.mee.2024.112281
G. Vinuesa , H. García , M.B. González , F. Campabadal , H. Castán , S. Dueñas
{"title":"Dynamics of set and reset processes in HfO2 -based bipolar resistive switching devices","authors":"G. Vinuesa ,&nbsp;H. García ,&nbsp;M.B. González ,&nbsp;F. Campabadal ,&nbsp;H. Castán ,&nbsp;S. Dueñas","doi":"10.1016/j.mee.2024.112281","DOIUrl":"10.1016/j.mee.2024.112281","url":null,"abstract":"<div><div>The temporal evolution of the set and reset processes in TiN/Ti/HfO<sub>2</sub>/W metal-insulator-metal devices exhibiting resistive switching behavior is investigated in depth. To this end, current transients were recorded by applying different voltages, which allowed us to change the conductance of the device. While both set and reset transitions are faster with increasing applied voltage, they clearly exhibit different time responses. The set transition is characterized by a monotonic increase in current after a sudden initial rise in its value, while the reset transition is characterized by a notably nonlinear response that resembles a sigmoidal function. We have successfully modeled the reset current transient with a bi-dose function and defined its time constant (Time-to-Reset) as the time where the current variation reaches its maximum value. Our findings show that varying the initial conditions of the reset process, such as increasing the temperature and/or decreasing the initial resistance value, significantly affect the reset transient, exponentially increasing the reset time constant value. This allows us to model its dependencies with the equation of a plane.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"296 ","pages":"Article 112281"},"PeriodicalIF":2.6,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142571762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel high-Q Lamé mode bulk acoustic resonator 新型高 Q 值拉美模式体声谐振器
IF 2.6 4区 工程技术
Microelectronic Engineering Pub Date : 2024-10-22 DOI: 10.1016/j.mee.2024.112279
Zeyu Wu , Bo Niu , Yiyi Hong , Junyuan Zhao , Yinfang Zhu , Jinling Yang
{"title":"A novel high-Q Lamé mode bulk acoustic resonator","authors":"Zeyu Wu ,&nbsp;Bo Niu ,&nbsp;Yiyi Hong ,&nbsp;Junyuan Zhao ,&nbsp;Yinfang Zhu ,&nbsp;Jinling Yang","doi":"10.1016/j.mee.2024.112279","DOIUrl":"10.1016/j.mee.2024.112279","url":null,"abstract":"<div><div>This study introduces a novel high-<em>Q</em> Lamé mode MEMS resonator, optimized through support beam structures and etching hole distributions to minimize anchor losses and thermal elastic dissipation (TED). Fabricated using a Silicon-On-Insulator (SOI) process, the resonators achieved <em>Q</em> values of 129,200 and 102,100 in different designs, demonstrating significant improvements in vacuum conditions and highlighting air damping as a key loss mechanism. Nonlinear analysis revealed material nonlinearity dominance. These findings offer valuable guidelines for developing high-end MEMS devices, such as low phase noise oscillators and high-resolution sensors, by showcasing substantial reductions in energy dissipation and enhanced <em>Q</em> factors through structural optimizations.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"295 ","pages":"Article 112279"},"PeriodicalIF":2.6,"publicationDate":"2024-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142535230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Nonvolatile logic gate and full adder based on tri-terminal oxide resistive switching devices 基于三端氧化物电阻开关器件的非易失性逻辑门和全加法器
IF 2.6 4区 工程技术
Microelectronic Engineering Pub Date : 2024-10-21 DOI: 10.1016/j.mee.2024.112280
Jifang Cao , Jiabao Ye , Tao Wang , Yong Ding , Ran Cheng , Dong Liu , Bing Chen
{"title":"Nonvolatile logic gate and full adder based on tri-terminal oxide resistive switching devices","authors":"Jifang Cao ,&nbsp;Jiabao Ye ,&nbsp;Tao Wang ,&nbsp;Yong Ding ,&nbsp;Ran Cheng ,&nbsp;Dong Liu ,&nbsp;Bing Chen","doi":"10.1016/j.mee.2024.112280","DOIUrl":"10.1016/j.mee.2024.112280","url":null,"abstract":"<div><div>Today's on-chip computing power is constrained by the “memory wall” and “power wall” caused by the Von Neumann bottleneck. As a potential solution, this work has developed nonvolatile logic gates based on field-effect tri-terminal oxide resistive switching memory devices (3T-RRAM). A compact circuit model using a polynomial control source (PCS) is proposed to describe the behavior of the fabricated 3T-RRAM. The 3T-RRAM can be regarded as a nonvolatile transmission gate for constructing nonvolatile logic gates. Additionally, a full adder with input storage functionality has been designed using only eight 3T-RRAMs (four nonvolatile logic gates), and a binarized neural network (BNN) based on 3T-RRAM logic gate arrays has been proposed. This demonstrates the great potential of nonvolatile logic gates in computing-in-memory applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"295 ","pages":"Article 112280"},"PeriodicalIF":2.6,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142539508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simulations of X-ray focusing by zone plates in rotationally symmetric optical field utilizing the matrix-free Finite Difference Beam Propagation Method 利用无矩阵有限差分光束传播法模拟旋转对称光场中区板聚焦 X 射线的过程
IF 2.6 4区 工程技术
Microelectronic Engineering Pub Date : 2024-10-19 DOI: 10.1016/j.mee.2024.112278
Hao Quan, Xujie Tong, Qingxin Wu, Qiucheng Chen, Yifang Chen
{"title":"Simulations of X-ray focusing by zone plates in rotationally symmetric optical field utilizing the matrix-free Finite Difference Beam Propagation Method","authors":"Hao Quan,&nbsp;Xujie Tong,&nbsp;Qingxin Wu,&nbsp;Qiucheng Chen,&nbsp;Yifang Chen","doi":"10.1016/j.mee.2024.112278","DOIUrl":"10.1016/j.mee.2024.112278","url":null,"abstract":"<div><div>We present the use of a finite difference method based on Crank-Nicholson scheme and recurrence scheme for computationally efficient simulation of the X-ray propagation through a zone plate. By introducing boundary and central conditions and by avoiding large matrix operations, the method achieves considerable speed, little memory occupation and low background noise. Accommodating refractive index profiles of arbitrary shape, it can be applied to assist optimizing X-ray zone plates and understanding focusing mechanism.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"295 ","pages":"Article 112278"},"PeriodicalIF":2.6,"publicationDate":"2024-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142535231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electron trapping in HfO2 layer deposited over a HF last treated silicon substrate 沉积在经过高频最后处理的硅衬底上的二氧化铪层中的电子陷阱
IF 2.6 4区 工程技术
Microelectronic Engineering Pub Date : 2024-10-09 DOI: 10.1016/j.mee.2024.112277
L. Sambuco Salomone , M.V. Cassani , M. Garcia-Inza , S. Carbonetto , E. Redin , F. Campabadal , A. Faigón
{"title":"Electron trapping in HfO2 layer deposited over a HF last treated silicon substrate","authors":"L. Sambuco Salomone ,&nbsp;M.V. Cassani ,&nbsp;M. Garcia-Inza ,&nbsp;S. Carbonetto ,&nbsp;E. Redin ,&nbsp;F. Campabadal ,&nbsp;A. Faigón","doi":"10.1016/j.mee.2024.112277","DOIUrl":"10.1016/j.mee.2024.112277","url":null,"abstract":"<div><div>Electron trapping in HfO<sub>2</sub>-based MOS structures was studied through pulsed capacitance-voltage (C-V) technique. 10 nm HfO<sub>2</sub> layer was deposited by atomic layer deposition over a HF last treated Si substrate. The C-V curves were observed to shift to positive voltages driven by the positive applied voltage along the pulses, consistent with electron trapping due to tunneling transitions between the substrate and pre-existing defects within the oxide and the subsequent lattice relaxation through electron-phonon interaction. The dependences of the voltage shift for a given capacitance value (<em>ΔV</em><sub><em>C</em></sub>) with stress bias and time, allowed to distinguish two mechanisms. An initial trapping process occurs for times shorter than the microsecond, probably associated with a thin non-stoichiometric SiO<sub>x</sub> interfacial layer, which is followed by a trapping process that starts after tens of μs and progressively slowed down, associated with traps within the HfO<sub>2</sub> layer. Numerical simulations yield for the HfO<sub>2</sub> traps an energy of 1.3 eV below the conduction band edge, decreasing exponentially with the distance from the Si interface with a characteristic length of 1.7 nm; and phonon and relaxation energies of 50 meV and 1 eV, respectively. These physical parameters are consistent with previous reports of electron trapping in HfO<sub>2</sub> layers deposited on a controlled interfacial layer, suggesting that trapping properties of defects inside the HfO<sub>2</sub> layer are insensitive to the treatment of the Si surface before HfO<sub>2</sub> deposition. On the other hand, the observed large initial trapping suggests that the non-controlled SiO<sub>x</sub> interfacial region is more defective than a controlled one.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"295 ","pages":"Article 112277"},"PeriodicalIF":2.6,"publicationDate":"2024-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142442774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of Superlattice Ferroelectric-Metal Field-effect Transistor for triple-level cell 3D NAND flash 为三级单元 3D NAND 闪存设计超晶格铁电-金属场效应晶体管
IF 2.6 4区 工程技术
Microelectronic Engineering Pub Date : 2024-09-24 DOI: 10.1016/j.mee.2024.112276
Sola Woo , Gihun Choe , Asif Islam Khan , Suman Datta , Shimeng Yu
{"title":"Design of Superlattice Ferroelectric-Metal Field-effect Transistor for triple-level cell 3D NAND flash","authors":"Sola Woo ,&nbsp;Gihun Choe ,&nbsp;Asif Islam Khan ,&nbsp;Suman Datta ,&nbsp;Shimeng Yu","doi":"10.1016/j.mee.2024.112276","DOIUrl":"10.1016/j.mee.2024.112276","url":null,"abstract":"<div><div>Superlattice ferroelectric-metal field-effect transistor (SL-FeMFET) based three-dimensional NAND architecture (3D NAND) is investigated for triple-level cell (TLC) operations. The SL-FeMFET shows a novel approach for designing the gate-stack using a superlattice of ferroelectric/dielectric/ferroelectric for achieving large memory window ∼3.48 V with program/erase voltage ±7 V for 3D NAND architecture. By TCAD modeling, we demonstrate TLC operation of SL-FeMFET with improving memory window and alleviating variability caused by floating metal layer in FeMFET structure. In addition, as the vertical gate stack increases from 256-layer to 512-layer, the read-out current with worst cases in seven read operations for TLC sensing are examined using page buffer circuit for sensing operation. The simulation results suggest that SL-FeMFET based 3D NAND architecture can operate 512-layer with sufficient sense margin for TLC operation.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"295 ","pages":"Article 112276"},"PeriodicalIF":2.6,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142318864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimizing dose parameters for enhanced maskless lithography in MoS2-based devices 优化剂量参数以增强基于 MoS2 器件的无掩模光刻技术
IF 2.6 4区 工程技术
Microelectronic Engineering Pub Date : 2024-09-19 DOI: 10.1016/j.mee.2024.112275
Hyun Min Park, Hyeon Woo Park, Muhammad Suleman, Minwook Kim, Sunil Kumar, Yongho Seo
{"title":"Optimizing dose parameters for enhanced maskless lithography in MoS2-based devices","authors":"Hyun Min Park,&nbsp;Hyeon Woo Park,&nbsp;Muhammad Suleman,&nbsp;Minwook Kim,&nbsp;Sunil Kumar,&nbsp;Yongho Seo","doi":"10.1016/j.mee.2024.112275","DOIUrl":"10.1016/j.mee.2024.112275","url":null,"abstract":"<div><div>Maskless lithography simplifies the fabrication process and reduces costs compared to electron beam (<em>E</em>-beam) lithography, making it a more efficient choice for patterning nano-devices. Maskless lithography presents a promising avenue for expediting device fabrication by eliminating the need for masks. This technique can streamline the production of basic electronic devices, offering an efficient and low-cost alternative to traditional lithographic methods, like <em>E</em>-beam lithography. This study utilized a 405 nm photodiode to achieve pattern-writing with a minimum linewidth of 1 μm. Exploring optimal parameters includes adjustments in beam intensity, scan speed, and step size. Maskless lithography was applied to 2D transition metal dichalcogenides (TMDCs) material, MoS<sub>2</sub>, to investigate their electrical transport characteristics. The fabricated device exhibits an ON/OFF ratio of ∼1.7 × 10<sup>6</sup> and a mobility of ∼0.833 cm<sup>2</sup>/V·s, indicating a high switching efficiency. The results demonstrate optimized maskless lithography's potential for swift and cost-effective fabrication, offering intermediate-resolution patterning capabilities.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"295 ","pages":"Article 112275"},"PeriodicalIF":2.6,"publicationDate":"2024-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142314978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High density nanofluidic channels by self-sealing for metallic nanoparticles detection 用于金属纳米粒子检测的自密封高密度纳米流体通道
IF 2.6 4区 工程技术
Microelectronic Engineering Pub Date : 2024-09-10 DOI: 10.1016/j.mee.2024.112264
Wentao Yuan , Qingxin Wu , Shuoqiu Tian , Jinyu Guo , Kangping Liu , Yifang Chen
{"title":"High density nanofluidic channels by self-sealing for metallic nanoparticles detection","authors":"Wentao Yuan ,&nbsp;Qingxin Wu ,&nbsp;Shuoqiu Tian ,&nbsp;Jinyu Guo ,&nbsp;Kangping Liu ,&nbsp;Yifang Chen","doi":"10.1016/j.mee.2024.112264","DOIUrl":"10.1016/j.mee.2024.112264","url":null,"abstract":"<div><p>High density nanofluidic channels were successfully fabricated by a novel process, nicknamed as self-sealing process, for the detection of metal nanoparticles dispersed in water using color changes excited by polarized electromagnetic waves. The permittivities of aqueous solutions with various concentrations of metal nanoparticles were calculated by a corrected plasma model. Systematic simulations using finite difference time domain method were carried out in investigating the detection capabilities of the nanofluidic channels for silver, beryllium and copper nanoparticles in water. The pronounced color shifts indicates that the channels possess high sensitivity in the metal nanoparticles detection. The designed nanofluidic channels were then fabricated by a direct flood deposition of a silica film on a pre-replicated hydrogen silsesquioxan (HSQ) grating using electron beam lithography (EBL). The self-sealing technique possesses advantages in simplified processing, encapsulation free and potential of multi-layer nanochannels.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"294 ","pages":"Article 112264"},"PeriodicalIF":2.6,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0167931724001333/pdfft?md5=7919c785cd0adb4939d756d37e60990d&pid=1-s2.0-S0167931724001333-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142163358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Etch of nano-TSV with smooth sidewall and excellent selection ratio for backside power delivery network 蚀刻出具有光滑侧壁和优异选择率的纳米 TSV,用于背面输电网络
IF 2.6 4区 工程技术
Microelectronic Engineering Pub Date : 2024-09-05 DOI: 10.1016/j.mee.2024.112265
Yang Wang , Ziyu Liu , Yabin Sun , Lin Chen , Qingqing Sun
{"title":"Etch of nano-TSV with smooth sidewall and excellent selection ratio for backside power delivery network","authors":"Yang Wang ,&nbsp;Ziyu Liu ,&nbsp;Yabin Sun ,&nbsp;Lin Chen ,&nbsp;Qingqing Sun","doi":"10.1016/j.mee.2024.112265","DOIUrl":"10.1016/j.mee.2024.112265","url":null,"abstract":"<div><p>Backside Power Delivery Network (BSPDN) is a crucial technology for integrated circuits at sub-3 nm technology nodes. The primary challenge resides in utilizing nano through silicon via (nano-TSV) to establish connections between the backside power network and buried power rails, thereby facilitating transistor powering. The key technology is to ensure a smooth sidewall morphology and prevent damage to buried power rails (BPR) due to over-etching. In this study, non-Bosch and Bosch techniques are compared using simulation. The results demonstrate that while the non-Bosch technique yields smooth sidewalls, it inevitably leads to over-etching, whereas Bosch effectively avoids over-etching. The etching of scallop-free nano-TSV is achieved by optimizing the Bosch process, which involves the use of inductively coupled plasma (ICP). Finally, metal filling of nano-TSV is successfully achieved. Thus, the nano-TSV etching method is established as viable for BSPDN.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"295 ","pages":"Article 112265"},"PeriodicalIF":2.6,"publicationDate":"2024-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142266227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development of an emulator of the sustainable energy harvesting pad system on a bike lane for charging lithium batteries 在自行车道上开发用于锂电池充电的可持续能量收集垫系统模拟器
IF 2.6 4区 工程技术
Microelectronic Engineering Pub Date : 2024-08-23 DOI: 10.1016/j.mee.2024.112262
Kazi Meharajul Kabir, Shuza Binzaid
{"title":"Development of an emulator of the sustainable energy harvesting pad system on a bike lane for charging lithium batteries","authors":"Kazi Meharajul Kabir,&nbsp;Shuza Binzaid","doi":"10.1016/j.mee.2024.112262","DOIUrl":"10.1016/j.mee.2024.112262","url":null,"abstract":"<div><p>In response to the urgent imperative of combating global warming and advancing sustainable energy solutions, an innovative approach has emerged, capitalizing on bicycles and road bike lane infrastructure. This solution integrates a Smart Lithium Battery Charging System with a Sustainable Energy Harvesting Pad (SEHP) designed for cyclists. The SEHP harnesses piezoelectric energy from mechanical vibrations and kinetic energy from lightweight vehicles. It produces clean, renewable electricity as an alternative to traditional power sources. Comprehensive assessments of the SEHP's energy generation performance at various proficiency levels have revealed impressive capabilities. An electronic emulator system is developed to support academic and research communities, simulating scenarios on bike lanes to efficiently charge 36.36 Wh lithium batteries at various cycling proficiency levels. The study involved specific circuit design, seamless integration with the custom Smart Lithium Battery Charging System, and optimization using Microcontroller hardware and software solutions. Practical prototypes verified the emulator's functionality and real-world applicability, making it an authentic replica of the SEHP's outcomes. This innovative technology enhances our understanding of SEHP and enables comparative analysis against other energy sources, contributing to a more sustainable future.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"294 ","pages":"Article 112262"},"PeriodicalIF":2.6,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142076794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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