Microelectronic Engineering最新文献

{"title":"Impact of low-temperature and low-pressure mild oxidation after plasma solidification on electrical properties and reliability in ultra-thin SiON MOSFETs","authors":"Qiao Teng ,&nbsp;Yongyu Wu ,&nbsp;Kai Xu ,&nbsp;Dawei Gao","doi":"10.1016/j.mee.2024.112213","DOIUrl":"https://doi.org/10.1016/j.mee.2024.112213","url":null,"abstract":"<div><p>The impact of different SiON manufacturing processes on performance and reliability behaviors has been investigated for the MOSFETs. The performance of devices composed of an ultrathin SiON film fabricated by the novel low-temperature and low-pressure mild oxidation after the plasma solidification (LLMOPS) method can be enhanced compared to conventional processes, which is attributed to the increased mobility. It is observed from secondary ion mass spectrometry analysis that the distribution of nitrogen with the LLMOPS process moves toward the upper surface of SiON. As a result, the p-MOSFET manufactured by the LLMOPS process exhibits lower electrical performance degradation during the NBTI stress, indicating that a reduction in nitrogen concentration at the Si/SiO₂ interface contributes to improving NBTI behavior. It is also demonstrated that the inhibition of NBTI phenomena enhances the frequency stability on the ring oscillator with circuit simulation. Thus, the LLMOPS process is a promising approach to improve the performance and reliability of MOSFETs in mass production.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"292 ","pages":"Article 112213"},"PeriodicalIF":2.6,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141607082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Feasibility study of fabricating 20 nm resolution dielectric Fresnel zone plates with ultrahigh aspect ratio for EUV optics","authors":"Qingxin Wu ,&nbsp;Qiucheng Chen ,&nbsp;Hao Quan ,&nbsp;Xujie Tong ,&nbsp;Jun Zhao ,&nbsp;Yifang Chen","doi":"10.1016/j.mee.2024.112227","DOIUrl":"https://doi.org/10.1016/j.mee.2024.112227","url":null,"abstract":"<div><p>EUV light optics are either reflective or diffractive due to the substantial absorption characteristics by almost all materials. Despite great successes in manufacturing integrated circuit chips, reflective EUV optics are still unfriendly to small-to-medium enterprise (SME) because of the enormous costs. Recently, diffractive EUV optics has come to the light in hopes to be able to establish manufacturing nanoscale products and inspecting nanoscale structures. Diffractive zone plates with high resolution in EUV wavelengths are urgently needed. This paper reports our latest success in developing 20 nm resolution zone plates for focusing and imaging in the EUV and soft X-ray regions. It firstly discusses the diffraction efficiency of FZPs tailored for 13.5 nm wavelength to decide the essential height of the zone plate. Then, Monte Carlo simulation method was used to figure out the achievable zone plate parameters by high-resolution electron beam lithography (EBL). Finally, this work systematically explored the viability of nanofabricating top-tier 20 nm resolution hydrogen silsesquioxane (HSQ) zone plates with the duty cycle ratio nearing 1:1 and the aspect ratio approaching 13:1 on 50 nm thick Si₃N₄ membranes.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"292 ","pages":"Article 112227"},"PeriodicalIF":2.6,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141484198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Rational design of CMUTs with annular electrodes for high ultrasonic emission via ESSE enabled stiffness adjustment","authors":"Zhikang Li ,&nbsp;Shiwang Zhang ,&nbsp;Yihe Zhao ,&nbsp;Shaohui Qin ,&nbsp;Shiyu Bai ,&nbsp;Jiawei Yuan ,&nbsp;Jie Li ,&nbsp;Zixuan Li ,&nbsp;Beibei Sun ,&nbsp;Qi Ma ,&nbsp;Xuan Shi ,&nbsp;Zilong Zhao ,&nbsp;Zheng Yuan ,&nbsp;Hefeng Qin ,&nbsp;Min Li ,&nbsp;Libo Zhao","doi":"10.1016/j.mee.2024.112224","DOIUrl":"https://doi.org/10.1016/j.mee.2024.112224","url":null,"abstract":"<div><p>Capacitive micromechanical ultrasonic transducers (CMUTs) with high transmitting acoustic pressure are in urgent demand in the rapidly growing field of air-coupled and therapeutic ultras ound. However, most current CMUTs can rarely balance the performance improvement and batch fabrication capacity, which severely impedes their practical applications. This paper proposes novel CMUTs with annular electrodes that can implement significant improvement in multiple performances while featuring a simple structure and batch fabrication feasibility. The annular electrode configurated between the membrane edge and center areas can effectively soften the corresponding-area membrane stiffness through electrostatic spring softening effects, and leave the stiffness of the membrane central area unchanged, finally enabling the membrane to produce a piston-like deformation, thus improving average displacement and output acoustic pressure. A finite element method was employed to analyze the effect of annular electrodes on the CMUT main performance. The results demonstrated that the novel structure could achieve prominent enhancement in multiple performances, such as an average to maximum displacement rate of 0.46 (about 0.32 for conventional CMUTs), maximum improvements of 300%, 255%, and 11% in average displacement, acoustic pressure, and electromechanical coupling coefficients compared to those of conventional ones. Deep analyses of the variation of the main performances including acoustic pressure, receiving sensitivity, and collapse voltage suggested that an optimal electrode coverage range of 36% ∼ 55% can be used to achieve relatively high comprehensive performances. Meanwhile, the proposed CMUTs feature a simpler structure and fabrication process in comparison with previous ones, showing great promise in air-coupled and therapeutic ultrasound applications.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"292 ","pages":"Article 112224"},"PeriodicalIF":2.6,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141484283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simulation of 2D ReS2/WSe2 based complementary field-effect transistors towards 1 nm technology node","authors":"Chi Zhang,&nbsp;Enlong Li,&nbsp;Hongmiao Zhou,&nbsp;Chenhao Xu,&nbsp;Wenwu Li","doi":"10.1016/j.mee.2024.112225","DOIUrl":"https://doi.org/10.1016/j.mee.2024.112225","url":null,"abstract":"<div><p>Advanced Integrated Circuit technology demands high-performance channel materials and innovative device architectures to sustain the scaling of field-effect transistors. In this study, we simulate the electrical performance of rhenium disulfide and tungsten diselenide nanosheet FETs (NSFETs) with gate lengths ranging from 12 nm to 8 nm using Technology Computer-Aided Design method. The simulated high performance including 393 μA/μm on-state current and over 10⁵ on/off ratio can meet the criteria for integrated circuit applications in the 1 nm technology node. Complementary FET (CFET) simulations are conducted through the vertical stacking of ReS₂ and WSe₂ NSFETs, exhibiting a small parasitic capacitance of 1.0 fF/μm, and notable noise margin (&gt;235 mV) at different process corners. The construction and performance simulation of Static Random-Access Memory (SRAM) is realized through CFET interconnection, involving the calculation of read current and read/write noise margin. This research offers a forward-looking analysis of performance metrics for future 2D materials-based NSFETs, CFETs, and SRAMs.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"292 ","pages":"Article 112225"},"PeriodicalIF":2.3,"publicationDate":"2024-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141325157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study on plasma-polymerized 1-(trimethylsilyl)pyrrolidine films deposited by plasma-enhanced chemical vapor deposition for use as a Cu diffusion barrier in multilevel metallization process","authors":"Chanyong Seo ,&nbsp;Namwuk Baek ,&nbsp;Shinwon Kang ,&nbsp;Gihoon Park ,&nbsp;Jihwan Cha ,&nbsp;Taesoon Jang ,&nbsp;Seonhee Jang ,&nbsp;Donggeun Jung","doi":"10.1016/j.mee.2024.112192","DOIUrl":"https://doi.org/10.1016/j.mee.2024.112192","url":null,"abstract":"<div><p>As integration continues in the modern semiconductor industry, copper (Cu) is used for metal lines and low dielectric constant (low-<em>k</em>) films are used for intermetal dielectrics (IMD) to reduce signal delays occurring in device interconnects. A diffusion barrier is essential between the Cu metal lines and the IMD to prevent Cu diffusion, and silicon carbon-nitride (SiCN) films with relatively low dielectric constants are being widely studied. In this study, SiCN films deposited from 1-(trimethylsilyl)pyrrolidine (TSPD) precursor by plasma-enhanced chemical vapor deposition (PECVD) were investigated for use as a Cu diffusion barrier in multilevel metallization process. This plasma-polymerized TSPD (ppTSPD) monolayer film as SiCN was deposited in plasma powers ranging from 15 to 30 W. The electrical properties of ppTSPD were measured and the chemical properties were analyzed by Fourier-transform infrared spectroscopy (FTIR). The dielectric constant increased with increased plasma power. The lowest dielectric constant of 3.70 and leakage current density at 1 MV/cm of 2.27<span><math><mo>×</mo></math></span>10⁻⁸ A/cm² were found for ppTSPD film deposited at 15 W. To verify the Cu diffusion barrier characteristics of the ppTSPD films, a ppTSPD/ppOMCTS bilayer was introduced by using plasma-polymerized octamethylcyclotetrasiloxane (ppOMCTS) as porous low-<em>k</em> SiCOH films. The time-dependent dielectric breakdown (TDDB) characteristic was enhanced around five times than ppOMCTS monolayer used as a reference. The ppTSPD was suggested for fabricating SiCN films for use as a Cu diffusion barrier in multilevel metallization process.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"291 ","pages":"Article 112192"},"PeriodicalIF":2.3,"publicationDate":"2024-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141294226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fractures of low-k materials in a RF package with integrated passive device based on TGV","authors":"Luchao Wu ,&nbsp;Lei Wang ,&nbsp;Jun Wang","doi":"10.1016/j.mee.2024.112195","DOIUrl":"https://doi.org/10.1016/j.mee.2024.112195","url":null,"abstract":"<div><p>The radio frequency (RF) chips and passive devices integrated on the through-glass-via (TGV) substrate meets the demands of miniaturization, high performance and low losses in the application. The RF chip and integrated passive devices (IPDs) are interconnected electrically by a redistribution layer (RDL) on the TGV substrate with the isolation low-k materials. The low-k materials, however, are susceptible to fracture during the thermal process in packaging due to their weak mechanical properties. In this study, the fractures of the low-k material were studied by experiments and the finite element analysis (FEA) for a RF package with integrated passive device based on TGV. The mechanical properties of the low-k material used in the FEA were tested by fabricating freestanding low-k films using microfabrication techniques. Then the fracture behaviors of the low-k material in the package and its impact factors under thermal loadings were examined. The impact factors, such as the initial defect location, direction and length, were investigated by evaluating the stress intensity factors (SIFs) at the defect tips. The results revealed that the most hazardous location in the low-k material is the region below the micro-joint of RF chip. The vertical defects along thickness in low-k film are more likely to propagate than horizontal ones. The SIF value increases linearly with the defect length both in heating and cooling conditions.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"291 ","pages":"Article 112195"},"PeriodicalIF":2.3,"publicationDate":"2024-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141294227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Chemical structure characteristics of flexible low-k SiCOH thin films etched by inductively coupled plasma-reactive ion etching process using FTIR and XPS spectra analysis","authors":"Thomas Poche ,&nbsp;William Wirth ,&nbsp;Seonhee Jang","doi":"10.1016/j.mee.2024.112221","DOIUrl":"https://doi.org/10.1016/j.mee.2024.112221","url":null,"abstract":"<div><p>Flexible low dielectric constant (low-<em>k</em>) SiCOH thin films were fabricated onto flexible indium tin oxide coated polyethylene naphthalate (ITO/PEN) substrates using plasma-enhanced chemical vapor deposition (PECVD) of a tetrakis(trimethylsilyloxy)silane (TTMSS) precursor. RF plasma powers of 20 and 60 W were utilized for the deposition. The <em>k</em>-values of the pristine SiCOH films deposited at 20 and 60 W were 2.46 and 2.00, respectively. Both films showed hydrophobic surfaces. An inductively coupled plasma-reactive ion etching (ICP-RIE) process was then performed on the flexible SiCOH thin films using CF₄, CF₄ + O₂, and CF₄ + Ar. The surface wettability of the films increased substantially following etching, with many of the etched films being considered hydrophilic. The Fourier transform infrared (FTIR) spectra of the pristine films identified four prominent absorption bands as CH_x stretching, Si-CH₃ bending, Si-O-Si stretching, and Si-(CH₃)_x stretching vibration modes. After the etching process, the peak area ratios of Si-O-Si stretching mode increased and those of Si-(CH₃)_x stretching mode decreased. The X-ray photoelectron spectroscopy (XPS) spectra analysis determined significant concentration of fluorine on the surface of the film following etching. From the high-resolution XPS scan, it was found that the peak intensity of the C1s and Si2p peaks decreased after etching process and the peak center of the F1s peak shifted depending on etching chemistry. The <em>k</em>-values of the films at 20 W were fairly consistent while those of the films at 60 W increased significantly following the etching process. The increase in <em>k</em>-value after etching for the films at 60 W correlated with surface hydrophilicity, increase in the refractive index, and change in the peak area ratios of Si-O-Si and Si-(CH₃)_x stretching modes in the FTIR spectra.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"292 ","pages":"Article 112221"},"PeriodicalIF":2.3,"publicationDate":"2024-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141291169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tuning of interface quality of Al/CeO2/Si device by post-annealing of sol-gel grown high-k CeO2 layers","authors":"G. Hari Priya ,&nbsp;S.K. Srivastava ,&nbsp;M.V. Shankar ,&nbsp;K.M.K. Srivatsa ,&nbsp;Amish G. Joshi ,&nbsp;Koteswara Rao Peta","doi":"10.1016/j.mee.2024.112212","DOIUrl":"https://doi.org/10.1016/j.mee.2024.112212","url":null,"abstract":"<div><p>A comprehensive study has been done on the influence of post-deposition annealing temperature on high-k cerium oxide (CeO₂) layer grown on n-type silicon (Si) substrate and its resultant interface states have been studied for Al/CeO₂/Si metal-oxide-semiconductor (MOS) devices. The high-k CeO₂ thin films were deposited by spin-coating and sintered at different annealing temperatures (<em>T</em>_<em>a</em>) in the range of 400–900 °C. The parameters such as fixed charge density (<em>Q</em>_<em>eff</em>), dielectric constant (<em>k</em>) of the layers, flat-band voltage (<em>V</em>_<em>FB</em>), interface defect density (D_<em>it</em>), etc., of the MOS device were evaluated from C<img>V and I-V measurements. A minimum value of flat band shift (∼0.05 V) with lower <em>Q</em>_<em>eff</em> (−4.81 × 10¹¹ C/cm²) have been achieved for the <em>T</em>_<em>a</em> of 600 °C. The <em>k</em> and <em>D</em>_<em>it</em> were evaluated to be 22 and 1.29 × 10¹² cm⁻², respectively at the <em>T</em>_<em>a</em> of 600 °C. In addition, the C<img>V measurements showed a very small hysteresis and very low frequency dispersion for the <em>T</em>_<em>a</em> of 600 °C sample. Energy distribution of defect states was evaluated and it was maximum towards the bottom of the conduction band. This shows that the 600 °C is the optimum annealing temperature, which results in high quality interface, and the electron affinity of the corresponding CeO₂ layers was found to be 3.29 eV as evaluated from ultraviolet photoelectron spectroscopy (UPS). Further, a maximum value of minority carrier lifetime (147 μs) has been achieved for the samples annealed at <em>T</em>_<em>a</em> of 400 °C, indicating that the post-annealing temperature plays a significant role on the properties of CeO₂ films deposited by sol-gel process. Thus, the present study demonstrates the possibility of sol-gel grown high k-CeO₂ layers suitable for MOS like devices.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"292 ","pages":"Article 112212"},"PeriodicalIF":2.3,"publicationDate":"2024-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141250520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A comparative study of C, N and Xe pre-amorphization implantation processes for improving the thermal stability of NiSi films","authors":"S. Guillemin,&nbsp;L. Lachal,&nbsp;P. Gergaud,&nbsp;A. Grenier,&nbsp;F. Nemouchi,&nbsp;F. Mazen,&nbsp;Ph. Rodriguez","doi":"10.1016/j.mee.2024.112210","DOIUrl":"https://doi.org/10.1016/j.mee.2024.112210","url":null,"abstract":"<div><p>In this paper, a comparative study of C-, N- and Xe-based pre-amorphization implantation (PAI) processes is proposed. The impact of the use of such processes on the agglomeration resistance and physical properties of the final Ni(<em>Pt</em>)Si layer, as well as the formation mechanisms via solid-state reactions and electrical performances via the transfer length measurement (TLM) method, is evaluated. It is shown that although all species are able to increase the agglomeration temperature of Ni(<em>Pt</em>)Si layers (up to more than 100 °C), the underlying mechanisms are different. For C- and N-based PAI processes a strong chemical effect is observed, while for Xe-based processes the amorphization depth plays an important role. Consequently, the beneficial effect of stabilizing Ni(<em>Pt</em>)Si layers at high temperatures using C- and N-based PAI processes has to be balanced with an increased layer resistivity (up to 30%) combined with a strong deterioration of the associated specific contact resistivity (which is multiplied by almost a factor 10). In this sense, Xe-based PAI processes seem to be a better option as they could allow to combine both requirements.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"291 ","pages":"Article 112210"},"PeriodicalIF":2.3,"publicationDate":"2024-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141090690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Neural networks based on in-sensor computing of optoelectronic memristor","authors":"Zhang Zhang ,&nbsp;Qifan Wang ,&nbsp;Gang Shi ,&nbsp;Yongbo Ma ,&nbsp;Jianmin Zeng ,&nbsp;Gang Liu","doi":"10.1016/j.mee.2024.112201","DOIUrl":"https://doi.org/10.1016/j.mee.2024.112201","url":null,"abstract":"<div><p>The separation band of perception, storage, and computation modules in vision systems based on traditional von Neumann architectures leads to latency and power consumption problems in data transmission, which severely limits the computational power. In recent years, in-sensor computing has gained significance in enhancing the computational performance of machine vision systems. It integrates sensing, storage and computation and is an important way to break out of the Von Neumann architecture. This study introduces an optoelectronic memristor-based image recognition algorithm to improve recognition efficiency by performing image feature extraction in a hardware array. The experimental results show that the network achieves the best accuracy of 93.26% after 30 epochs, and the loss of accuracy after weight quantization is about 1%.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"291 ","pages":"Article 112201"},"PeriodicalIF":2.3,"publicationDate":"2024-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140910400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}