{"title":"Origin of charges in bulk Si:HfO2 FeFET probed by nanosecond polarization measurements","authors":"","doi":"10.1016/j.mee.2024.112284","DOIUrl":"10.1016/j.mee.2024.112284","url":null,"abstract":"<div><div>FeFET technology offers the potential for fast, energy-efficient, low-cost, and high-capacity non-volatile memory and neuromorphic devices. However, charge trapping significantly affects device operation, leading to issues like read-after-write delay and limited endurance. Therefore, a detailed understanding of charge trapping, charge origin and its role in polarization switching is crucial. In this study, we uncover the spectral energy origin of polarization charges in Si:HfO<sub>2</sub> N-FeFET by probing electron (conduction band) and hole (valence band) currents separately during polarization-voltage (<em>P–V</em>) measurements. We utilize a fast (∼20 ns) and modified positive-up-negative-down (PUND) technique, where bulk, source, and drain currents of the FeFET are measured separately. The nanosecond timescale of the measurement results in measurable currents in FeFETs having dimensions of a few μm. This charge separation shows that program (PRG, <em>V</em><sub>GS</sub> > 0) charge originates from the conduction band, whereas erase (ERS, <em>V</em><sub>GS</sub> < 0) originates from the valence band of the Si. Moreover, the polarization curve (<em>P–V</em>) of a cycled device (following 5000 PRG/ERS pulses) shows measurable hysteresis even though the transfer curve of the same device shows that the memory window in the threshold voltage vanishes. Therefore, the FeFET polarization state can be read without delay after write operation by the fast PUND measurement, both for pristine and cycled FeFETs.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.6,"publicationDate":"2024-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142593419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On the mechanical properties of ultrathin titanium nitride films under different gas ratios of PVD process","authors":"","doi":"10.1016/j.mee.2024.112283","DOIUrl":"10.1016/j.mee.2024.112283","url":null,"abstract":"<div><div>Titanium Nitride (TiN<sub>x</sub>) thin film has numerous applications in semiconductors, nanotechnology, and various aspects of daily life. This study presents an approach to adjusting the mechanical properties of TiN<sub>x</sub> ultrathin films, including Young's modulus, residual stress, and coefficients of thermal expansion (CTE), by varying the gas ratio of N<sub>2</sub> and Ar during the Physical Vapor Deposition (PVD) process (DC magnetron sputtering). In the experiment, TiN<sub>x</sub> films with three different gas ratios R<sub>N</sub> (= N<sub>2</sub>/(N<sub>2</sub> + Ar)) were investigated. To demonstrate the feasibility of this approach, TiN<sub>x</sub> films with different R<sub>N</sub> values (0.3, 0.5, and 0.8) were deposited on SiO<sub>2</sub> beams to form composite test cantilevers. Measurements reveal significant changes (ranging from 33 % to 2-fold) in Young's modulus, residual stress, and CTE of the TiN<sub>x</sub> films by varying the gas ratio during the PVD process. As a result, this study provides a straightforward approach and guidelines for users to tailor TiN<sub>x</sub> films according to specific application requirements.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.6,"publicationDate":"2024-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142586678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 10 kHz bandwidth low-power active negative feedback front-end amplifier based on unipolar IZO TFT technology","authors":"","doi":"10.1016/j.mee.2024.112282","DOIUrl":"10.1016/j.mee.2024.112282","url":null,"abstract":"<div><div>In this paper, we present a wide-bandwidth low-power front-end amplifier based on thin-film transistors (TFTs). The amplifier with the active negative feedback structure in the form of the common source is proposed, which achieves wide bandwidth under the condition of low power consumption. In addition, the capacitor bootstrap load structure is used in the core operational transconductance amplifier (OTA) circuit, which improves the loop gain. The proposed amplifier adopts the 10 μm channel length unipolar n-type indium‑zinc-oxide (IZO) TFT technology, with an area of 2 mm<sup>2</sup>. The test results show a gain of 36.3 dB, a bandwidth of 10 kHz, and a power consumption of 0.04 mW at a supply voltage of 10 V. The proposed amplifier is advanced in bandwidth, power, and area, has successfully obtained and amplified real-time electrocardiogram (ECG) and electromyography (EMG) signals, and also has excellent noise efficiency factor (NEF) and power efficiency factor (PEF). Therefore, the design has potential in the field of flexible bioelectrical signal detection and other wearable electronic devices in the future.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.6,"publicationDate":"2024-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142586679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dynamics of set and reset processes in HfO2 -based bipolar resistive switching devices","authors":"","doi":"10.1016/j.mee.2024.112281","DOIUrl":"10.1016/j.mee.2024.112281","url":null,"abstract":"<div><div>The temporal evolution of the set and reset processes in TiN/Ti/HfO<sub>2</sub>/W metal-insulator-metal devices exhibiting resistive switching behavior is investigated in depth. To this end, current transients were recorded by applying different voltages, which allowed us to change the conductance of the device. While both set and reset transitions are faster with increasing applied voltage, they clearly exhibit different time responses. The set transition is characterized by a monotonic increase in current after a sudden initial rise in its value, while the reset transition is characterized by a notably nonlinear response that resembles a sigmoidal function. We have successfully modeled the reset current transient with a bi-dose function and defined its time constant (Time-to-Reset) as the time where the current variation reaches its maximum value. Our findings show that varying the initial conditions of the reset process, such as increasing the temperature and/or decreasing the initial resistance value, significantly affect the reset transient, exponentially increasing the reset time constant value. This allows us to model its dependencies with the equation of a plane.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.6,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142571762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A novel high-Q Lamé mode bulk acoustic resonator","authors":"","doi":"10.1016/j.mee.2024.112279","DOIUrl":"10.1016/j.mee.2024.112279","url":null,"abstract":"<div><div>This study introduces a novel high-<em>Q</em> Lamé mode MEMS resonator, optimized through support beam structures and etching hole distributions to minimize anchor losses and thermal elastic dissipation (TED). Fabricated using a Silicon-On-Insulator (SOI) process, the resonators achieved <em>Q</em> values of 129,200 and 102,100 in different designs, demonstrating significant improvements in vacuum conditions and highlighting air damping as a key loss mechanism. Nonlinear analysis revealed material nonlinearity dominance. These findings offer valuable guidelines for developing high-end MEMS devices, such as low phase noise oscillators and high-resolution sensors, by showcasing substantial reductions in energy dissipation and enhanced <em>Q</em> factors through structural optimizations.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.6,"publicationDate":"2024-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142535230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Nonvolatile logic gate and full adder based on tri-terminal oxide resistive switching devices","authors":"","doi":"10.1016/j.mee.2024.112280","DOIUrl":"10.1016/j.mee.2024.112280","url":null,"abstract":"<div><div>Today's on-chip computing power is constrained by the “memory wall” and “power wall” caused by the Von Neumann bottleneck. As a potential solution, this work has developed nonvolatile logic gates based on field-effect tri-terminal oxide resistive switching memory devices (3T-RRAM). A compact circuit model using a polynomial control source (PCS) is proposed to describe the behavior of the fabricated 3T-RRAM. The 3T-RRAM can be regarded as a nonvolatile transmission gate for constructing nonvolatile logic gates. Additionally, a full adder with input storage functionality has been designed using only eight 3T-RRAMs (four nonvolatile logic gates), and a binarized neural network (BNN) based on 3T-RRAM logic gate arrays has been proposed. This demonstrates the great potential of nonvolatile logic gates in computing-in-memory applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.6,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142539508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simulations of X-ray focusing by zone plates in rotationally symmetric optical field utilizing the matrix-free Finite Difference Beam Propagation Method","authors":"","doi":"10.1016/j.mee.2024.112278","DOIUrl":"10.1016/j.mee.2024.112278","url":null,"abstract":"<div><div>We present the use of a finite difference method based on Crank-Nicholson scheme and recurrence scheme for computationally efficient simulation of the X-ray propagation through a zone plate. By introducing boundary and central conditions and by avoiding large matrix operations, the method achieves considerable speed, little memory occupation and low background noise. Accommodating refractive index profiles of arbitrary shape, it can be applied to assist optimizing X-ray zone plates and understanding focusing mechanism.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.6,"publicationDate":"2024-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142535231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Electron trapping in HfO2 layer deposited over a HF last treated silicon substrate","authors":"","doi":"10.1016/j.mee.2024.112277","DOIUrl":"10.1016/j.mee.2024.112277","url":null,"abstract":"<div><div>Electron trapping in HfO<sub>2</sub>-based MOS structures was studied through pulsed capacitance-voltage (C-V) technique. 10 nm HfO<sub>2</sub> layer was deposited by atomic layer deposition over a HF last treated Si substrate. The C-V curves were observed to shift to positive voltages driven by the positive applied voltage along the pulses, consistent with electron trapping due to tunneling transitions between the substrate and pre-existing defects within the oxide and the subsequent lattice relaxation through electron-phonon interaction. The dependences of the voltage shift for a given capacitance value (<em>ΔV</em><sub><em>C</em></sub>) with stress bias and time, allowed to distinguish two mechanisms. An initial trapping process occurs for times shorter than the microsecond, probably associated with a thin non-stoichiometric SiO<sub>x</sub> interfacial layer, which is followed by a trapping process that starts after tens of μs and progressively slowed down, associated with traps within the HfO<sub>2</sub> layer. Numerical simulations yield for the HfO<sub>2</sub> traps an energy of 1.3 eV below the conduction band edge, decreasing exponentially with the distance from the Si interface with a characteristic length of 1.7 nm; and phonon and relaxation energies of 50 meV and 1 eV, respectively. These physical parameters are consistent with previous reports of electron trapping in HfO<sub>2</sub> layers deposited on a controlled interfacial layer, suggesting that trapping properties of defects inside the HfO<sub>2</sub> layer are insensitive to the treatment of the Si surface before HfO<sub>2</sub> deposition. On the other hand, the observed large initial trapping suggests that the non-controlled SiO<sub>x</sub> interfacial region is more defective than a controlled one.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.6,"publicationDate":"2024-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142442774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of Superlattice Ferroelectric-Metal Field-effect Transistor for triple-level cell 3D NAND flash","authors":"","doi":"10.1016/j.mee.2024.112276","DOIUrl":"10.1016/j.mee.2024.112276","url":null,"abstract":"<div><div>Superlattice ferroelectric-metal field-effect transistor (SL-FeMFET) based three-dimensional NAND architecture (3D NAND) is investigated for triple-level cell (TLC) operations. The SL-FeMFET shows a novel approach for designing the gate-stack using a superlattice of ferroelectric/dielectric/ferroelectric for achieving large memory window ∼3.48 V with program/erase voltage ±7 V for 3D NAND architecture. By TCAD modeling, we demonstrate TLC operation of SL-FeMFET with improving memory window and alleviating variability caused by floating metal layer in FeMFET structure. In addition, as the vertical gate stack increases from 256-layer to 512-layer, the read-out current with worst cases in seven read operations for TLC sensing are examined using page buffer circuit for sensing operation. The simulation results suggest that SL-FeMFET based 3D NAND architecture can operate 512-layer with sufficient sense margin for TLC operation.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.6,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142318864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimizing dose parameters for enhanced maskless lithography in MoS2-based devices","authors":"","doi":"10.1016/j.mee.2024.112275","DOIUrl":"10.1016/j.mee.2024.112275","url":null,"abstract":"<div><div>Maskless lithography simplifies the fabrication process and reduces costs compared to electron beam (<em>E</em>-beam) lithography, making it a more efficient choice for patterning nano-devices. Maskless lithography presents a promising avenue for expediting device fabrication by eliminating the need for masks. This technique can streamline the production of basic electronic devices, offering an efficient and low-cost alternative to traditional lithographic methods, like <em>E</em>-beam lithography. This study utilized a 405 nm photodiode to achieve pattern-writing with a minimum linewidth of 1 μm. Exploring optimal parameters includes adjustments in beam intensity, scan speed, and step size. Maskless lithography was applied to 2D transition metal dichalcogenides (TMDCs) material, MoS<sub>2</sub>, to investigate their electrical transport characteristics. The fabricated device exhibits an ON/OFF ratio of ∼1.7 × 10<sup>6</sup> and a mobility of ∼0.833 cm<sup>2</sup>/V·s, indicating a high switching efficiency. The results demonstrate optimized maskless lithography's potential for swift and cost-effective fabrication, offering intermediate-resolution patterning capabilities.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.6,"publicationDate":"2024-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142314978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}