Microelectronic Engineering最新文献

Variation-robust CMOS monostable multivibrator-based spiking neuron and spiking neural networks 基于变鲁棒CMOS单稳态多振子的脉冲神经元和脉冲神经网络

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-06-01 Epub Date: 2026-01-12 DOI: 10.1016/j.mee.2025.112444

Maleeha Abdul Azeez, Dhanaraj K.J.

{"title":"Variation-robust CMOS monostable multivibrator-based spiking neuron and spiking neural networks","authors":"Maleeha Abdul Azeez, Dhanaraj K.J.","doi":"10.1016/j.mee.2025.112444","DOIUrl":"10.1016/j.mee.2025.112444","url":null,"abstract":"<div><div>Spiking Neural Networks (SNNs) are a class of Artificial Neural Networks (ANNs) that process information encoded in spike trains. Hardware implementations of spiking neurons, the building blocks of SNNs, reveal that SNNs can be realized as low-power and high-density neural networks. In this work, a spiking neuron design realized using a CMOS-based monostable multivibrator circuit is proposed. Performance comparisons with similar spiking neuron designs show that the proposed neuron exhibits high robustness to hardware variations in addition to its low power, low area, and low latency characteristics. The ability to operate over a wide range of spike rates enables deployment of the neuron in a wide variety of applications. SNNs using rate encoding and TTFS (Time-To-First-Spike) encoding designed with the proposed neuron exhibit better performance results in comparison with those realized using other similar designs in the simulation studies. The possibility of using the neuron for large-scale SNNs is also explored. Post-layout simulations of the neuron and two SNNs built with the neuron also show high robustness, conforming with the corresponding results from the pre-layout simulations. With an active footprint area of <span><math><mrow><mn>33</mn><mspace></mspace><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> and energy per spike as low as 100 fJ, the monostable multivibrator-based neuron proves to be a simple, compact, energy-efficient and variation-tolerant spiking neuron, which is a good candidate for building diverse SNNs.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112444"},"PeriodicalIF":3.1,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145978972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A product qualification vehicle (PQV) for accelerated yield learning and efficient fault isolation in 28 nm HKMG technologies by capturing LDE and BEOL weak patterns 通过捕获LDE和BEOL弱模式，在28nm HKMG技术中加速良率学习和有效故障隔离的产品认证工具（PQV）

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-06-01 Epub Date: 2026-01-21 DOI: 10.1016/j.mee.2026.112452

Enjing Cai , Limin Zhou , Qiang Chen , David Wei Zhang , Qingqing Sun , Hao Zhu

{"title":"A product qualification vehicle (PQV) for accelerated yield learning and efficient fault isolation in 28 nm HKMG technologies by capturing LDE and BEOL weak patterns","authors":"Enjing Cai , Limin Zhou , Qiang Chen , David Wei Zhang , Qingqing Sun , Hao Zhu","doi":"10.1016/j.mee.2026.112452","DOIUrl":"10.1016/j.mee.2026.112452","url":null,"abstract":"<div><div>As CMOS technology scales to the 28 nm node and beyond, systematic yield limiters such as layout-dependent effects (LDE) and back-end-of-line (BEOL) weak patterns induced by routing congestion become increasingly pronounced. This creates a significant “SRAM-to-Product” gap, where conventional static random-access memory (SRAM)-based process monitoring inadequately reflects actual product performance. Moreover, the inherent time-consuming and resource-intensive nature of failure analysis (FA) for product-like monitors, primarily due to their dependency on complex electronic design automation (EDA)-based diagnostics, constitutes a severe FA bottleneck. In this paper, we present a novel product qualification vehicle (PQV), implemented on a 28 nm high-k/metal gate (HKMG) platform, that effectively bridges this critical gap. The PQV incorporates dedicated arrays of bit-cells constructed from standard logic gates, strategically designed to authentically replicate product-level LDE and BEOL stressors through a realistic place & route (P&R) flow. Crucially, it features an EDA-less diagnostic engine that provides direct physical coordinates of failing bits, thereby streamlining fault isolation by completely eliminating the need for conventional EDA tools. Silicon validation demonstrates that the PQV successfully captures critical LDE-induced functional failures and BEOL via-open defects systematically missed by conventional SRAMs. This methodology accelerates the fault-to-physical root-cause diagnosis cycle by over twelve times, facilitating rapid process learning and substantially reducing time-to-market.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112452"},"PeriodicalIF":3.1,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146090391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A new subthreshold half-select free SRAM with dynamic feedback cut-off for low-power and high speed applications 具有动态反馈截止的新型亚阈值半选择自由SRAM，适用于低功耗和高速应用

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-06-01 Epub Date: 2026-01-01 DOI: 10.1016/j.mee.2025.112438

Mohammadhasan jali , S. Mohammadali Zanjani , Mehdi Dolatshahi , Behrang Barekatain

{"title":"A new subthreshold half-select free SRAM with dynamic feedback cut-off for low-power and high speed applications","authors":"Mohammadhasan jali , S. Mohammadali Zanjani , Mehdi Dolatshahi , Behrang Barekatain","doi":"10.1016/j.mee.2025.112438","DOIUrl":"10.1016/j.mee.2025.112438","url":null,"abstract":"<div><div>This paper presents a novel 10 T static random-access memory (SRAM) cell designed for low-power, high-speed, and half-selected disturbance-free applications, featuring a differential write operation and a separated single-ended read operation. To reduce power consumption and enhance write stability, one of the back-to-back inverters is dynamically based on bit line value, removed from the circuit during the write phase, without the need for auxiliary circuitry. This functionality is implemented using stacked transistors in a single inverter, which also reduces leakage power. Moreover, subthreshold operation, along with dynamic threshold techniques, is employed to achieve additional power reduction. The proposed cell is evaluated through HSPICE simulations using 32 nm carbon nanotube field-effect transistor (CNFET) technology. Monte Carlo analysis shows that the write margin (WM), read static noise margin (RSNM), and hold static noise margin (HSNM) are 139.9 mV, 65.4 mV, and 63.9 mV, respectively. The write and read access times are 228.2 ps and 209.8 ps, respectively. The maximum write power consumption is 3.8 nW, while the read and leakage power are 10.4 nW and 252.2 pW, respectively. The minimum operating voltage is 150 mV, with an RSNM of 26 mV. The proposed 10 T SRAM cell occupies an area of about 0.161 μm<sup>2</sup>.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112438"},"PeriodicalIF":3.1,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145871679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effect of thermally-induced cracks on the mechanical and electrical behaviour of TGVs 热致裂纹对tgv力学和电学性能的影响

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-06-01 Epub Date: 2025-12-30 DOI: 10.1016/j.mee.2025.112441

Mugdha Sharma , Pradeep Dixit , Sanjeev Manhas

{"title":"Effect of thermally-induced cracks on the mechanical and electrical behaviour of TGVs","authors":"Mugdha Sharma , Pradeep Dixit , Sanjeev Manhas","doi":"10.1016/j.mee.2025.112441","DOIUrl":"10.1016/j.mee.2025.112441","url":null,"abstract":"<div><div>Through-glass vias (TGVs) are gaining importance in 2.5D/3D packaging due to their low electrical loss, dimensional stability, and panel-level manufacturability. However, the large mismatch in coefficient of thermal expansion (CTE) between copper(Cu) and glass induces significant thermo-mechanical stresses during temperature variations, leading to crack initiation, energy release, and electrical degradation. In this work, a coupled finite element method (FEM) and fracture mechanics framework is developed to analyze the reliability of Cu-filled TGVs. The study evaluates stress distribution, deformation, and current density in the presence of cracks positioned at different locations within the via and along the Cu–glass interface. The fracture driving force is quantified using the Energy Release Rate (ERR), with analytical formulations validated against FEM-based J-integral calculations. Results show that ERR scales linearly with via diameter and quadratically with temperature change magnitude, with peak values occurring when the crack length is approximately one-fourth of the via diameter. Substrate material strongly influences reliability, as fused silica produces the highest stresses and ERR, while ceramic glass gives better reliability. The introduction of polymer buffer layers significantly reduces stress in the TGV, demonstrating their effectiveness in mitigating mismatch-induced failures. Altogether, the combined FEM–ERR framework provides a unified basis for linking stress, fracture, and electrical degradation, and offers practical design guidelines for optimizing TGV-based interposers.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112441"},"PeriodicalIF":3.1,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145940571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Variability in HfO2-based memristors under pulse operation 脉冲操作下hfo2基忆阻器的可变性

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-06-01 Epub Date: 2026-01-22 DOI: 10.1016/j.mee.2026.112445

D. Maldonado , C. Acal , H. Ortiz , F. Navas-Gomez , A. Cantudo , C. Wenger , E. Pérez , J.B. Roldán

{"title":"Variability in HfO2-based memristors under pulse operation","authors":"D. Maldonado , C. Acal , H. Ortiz , F. Navas-Gomez , A. Cantudo , C. Wenger , E. Pérez , J.B. Roldán","doi":"10.1016/j.mee.2026.112445","DOIUrl":"10.1016/j.mee.2026.112445","url":null,"abstract":"<div><div>We have studied device-to-device variability in TiN/Ti/HfO<sub>2</sub>/TiN devices under pulse operation. We measured extensively memristive devices that are CMOS integrated with different pulse trains, changing the pulse width and amplitude for groups of more than one hundred devices. The statistical parameters of the measured current were extracted to better understand the device physics under the pulse operation regime. An analytical model to describe synaptic depression and potentiation behavior in the device conductance is introduced, it fits accurately the means of the current data for all the pulse trains under study. In addition, an explanation of the measurements is enlightened with kinetic Monte Carlo simulations that allow the study of resistive switching at the atomic level. Finally, the probability distribution functions of the measured currents in some of the pulses within the pulse series employed are analyzed to extract the probability distribution that works better. A proposal for the implementation of device-to-device variability in the Stanford models is introduced.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112445"},"PeriodicalIF":3.1,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146078754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An electromagnetic study of scalability of Si3N4 optical waveguides for 3D nanophotonic integration with CMOS electronics in AI era 人工智能时代CMOS电子器件三维纳米光子集成Si3N4光波导可扩展性的电磁研究

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-06-01 Epub Date: 2026-01-02 DOI: 10.1016/j.mee.2025.112440

Wenli Zhou , Rui (Ray) Yao , Sang Lam

{"title":"An electromagnetic study of scalability of Si3N4 optical waveguides for 3D nanophotonic integration with CMOS electronics in AI era","authors":"Wenli Zhou , Rui (Ray) Yao , Sang Lam","doi":"10.1016/j.mee.2025.112440","DOIUrl":"10.1016/j.mee.2025.112440","url":null,"abstract":"<div><div>We report computational electromagnetic (EM) investigation into the planar optical waveguide with the silicon nitride (Si<sub>3</sub>N<sub>4</sub>) core scaled down from 800 nm to 60 nm. The surrounding cladding of silicon dioxide (SiO<sub>2</sub>) is at least 2 μm thick. With the CMOS-compatible Si<sub>3</sub>N<sub>4</sub> optical waveguide constructed on a resistive silicon (Si) substrate, EM fields of the whole structure are computed by solving Maxwell's equations based on the finite element method (FEM). Electric field profiles of the fundamental mode are obtained at 900 nm wavelength (λ) which is shorter than the bandgap wavelength of Si and hence optical loss in the substrate. It is found that in scaling down the Si<sub>3</sub>N<sub>4</sub> core to sub-wavelength thickness (i.e. less than (λ/<em>n</em>)), the evanescent electric field penetrates strongly through the SiO<sub>2</sub> under-cladding into the resistive substrate. The field penetration is even stronger for core thickness of 100 nm and 60 nm, which are equivalent to 0.22(λ/<em>n</em>) and 0.13(λ/<em>n</em>) respectively. Apart from using SiO<sub>2</sub> cladding of 4 μm or thicker, doubling the core width to increase the width-to-thickness ratio would provide alleviation. The results provide helpful guidelines about the Si<sub>3</sub>N<sub>4</sub> thickness, width and spatial separation, in the design and fabrication of nanophotonic devices and circuits for potential 3D integration with CMOS electronics built on the Si substrate.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"304 ","pages":"Article 112440"},"PeriodicalIF":3.1,"publicationDate":"2026-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146078665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Research on evaluation method of data retention capability of STT-MRAM chips STT-MRAM芯片数据保留能力评估方法研究

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-03-01 Epub Date: 2025-11-25 DOI: 10.1016/j.mee.2025.112427

Jiejie Sun , Meining Ji , Hongguang Shen , Chuanpeng Jiang , Chao Wang , Meng Zhang , Kaihua Cao , Bi Wang , Haibo Ye

{"title":"Research on evaluation method of data retention capability of STT-MRAM chips","authors":"Jiejie Sun , Meining Ji , Hongguang Shen , Chuanpeng Jiang , Chao Wang , Meng Zhang , Kaihua Cao , Bi Wang , Haibo Ye","doi":"10.1016/j.mee.2025.112427","DOIUrl":"10.1016/j.mee.2025.112427","url":null,"abstract":"<div><div>Data retention time, a crucial reliability parameter in spin-transfer torque magnetic random access memory (STT-MRAM), characterizes the capability to maintain stable data storage time. Methods for evaluating data retention time often face the issues of excessive test time and limited precision. This study investigates the data retention capability of STT-MRAM chips by using high-temperature acceleration and magnetic-field acceleration methods, which significantly enhance both testing efficiency and accuracy. The two acceleration methods show high consistency in predicting <em>E</em><sub>Bmeff</sub> and <em>Δ</em><sub>eff</sub>, with a relative deviation of only 10 % at −25 °C. Furthermore, the observed dependence of <em>E</em><sub>Beff</sub> on the magnetic field aligns well with theoretical predictions derived from the domain wall model. Experimental results show that STT-MRAM chips can achieve a data retention time exceeding 20 years at 105 °C, fulfilling the stringent reliability criteria required for industrial-grade memory applications. These findings provide critical experimental verification and technical insights to support the integration of STT-MRAM into next-generation memory architectures.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112427"},"PeriodicalIF":3.1,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145623074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Graphene nanoribbon interconnects for RF sensing: Modeling and performance analysis using ring oscillators 用于射频传感的石墨烯纳米带互连：环形振荡器的建模和性能分析

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-03-01 Epub Date: 2026-01-03 DOI: 10.1016/j.mee.2025.112442

Sandip Bhattacharya , Tan Cher Ming , Subhajit Das , Abir Chattopadhyay

{"title":"Graphene nanoribbon interconnects for RF sensing: Modeling and performance analysis using ring oscillators","authors":"Sandip Bhattacharya , Tan Cher Ming , Subhajit Das , Abir Chattopadhyay","doi":"10.1016/j.mee.2025.112442","DOIUrl":"10.1016/j.mee.2025.112442","url":null,"abstract":"<div><div>In the proposed work, our SPICE-compatible compact RF model of multi-layer graphene nanoribbon (MLGNR) interconnect is interfaced with 3-stage ring oscillator to validate the circuit performance of MLGNR interconnect in on-chip RF sensing applications. The 16 nm CMOS process technology PTM model has been paired with 16 nm MLGNR interconnect considering the ITRS-13 to design, validate and analyze power consumption, propagation delay, and noise characteristics of the basic ring oscillator in high-frequency generation for RF sensing applications. The comparative performance with conventional copper interconnect and side-contact MLGNR interconnect is analyzed. Our study revealed that the use of side-contact GNR (SC-GNR) with a mean free path (MFP) of near 1000 nm outperforms other interconnect materials such as Cu, SC-GNR (MFP = 300 nm), and SC-GNR (MFP = 419 nm). Specifically, SC-GNR with MFP of 1000 nm can achieve a max frequency of 4.8 GHz, making it highly suitable for high-speed data processing while consuming ∼2–3 times less power and exhibiting ∼2.5–3.5 times less delay compared to alternative interconnects in RF sensing applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112442"},"PeriodicalIF":3.1,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145925214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Comprehensive statistical analysis of random telegraph noise: Impact of gate voltage, temperature, and Bias time 随机电报噪声的综合统计分析：栅极电压、温度和偏置时间的影响

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-03-01 Epub Date: 2025-12-13 DOI: 10.1016/j.mee.2025.112437

J. Martin-Martinez , N. Baghban-Bousari , R. Castro-Lopez , D. Eric , E. Roca , R. Rodriguez , M. Porti , F.V. Fernandez , M. Nafria

引用次数: 0

Asynchronous real-time learning in Spiking Neural Network using 3-terminal Resistance Random Access Memory 基于3端电阻随机存取存储器的脉冲神经网络异步实时学习

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-03-01 Epub Date: 2025-11-22 DOI: 10.1016/j.mee.2025.112429

Harshvardhan Singh , Nirmal Solanki , Jaskirat Singh Maskeen , Shalu Saini , Madhav Pathak , Sandip Lashkare

{"title":"Asynchronous real-time learning in Spiking Neural Network using 3-terminal Resistance Random Access Memory","authors":"Harshvardhan Singh , Nirmal Solanki , Jaskirat Singh Maskeen , Shalu Saini , Madhav Pathak , Sandip Lashkare","doi":"10.1016/j.mee.2025.112429","DOIUrl":"10.1016/j.mee.2025.112429","url":null,"abstract":"<div><div>Spiking Neural Networks (SNNs) inspired by the human brain are promising alternative to solve real-life complex problems, such as pattern recognition at low energy consumption. A key approach to implementing SNNs involves using a Resistance Random Access Memory (RRAM) crossbar array to simulate synaptic weights, which can have multi-step resistance states suitable for processing analog signals. However, a major hurdle with traditional 2-terminal RRAMs is the “read–write dilemma”: the low voltage needed for a non-destructive read operation conflicts with the high voltage required for a write operation, making simultaneous, real-time learning challenging. Current solutions to this problem, such as time or frequency division multiplexing and separate read/write arrays, increase the circuit’s complexity, size, or operation time. This paper proposes a novel solution using a recently developed 3-terminal (3T) <span><math><mrow><msub><mrow><mtext>Pr</mtext></mrow><mrow><mn>0</mn><mo>.</mo><mn>7</mn></mrow></msub><msub><mrow><mtext>Ca</mtext></mrow><mrow><mn>0</mn><mo>.</mo><mn>3</mn></mrow></msub><msub><mrow><mtext>MnO</mtext></mrow><mrow><mn>3</mn></mrow></msub></mrow></math></span> (PCMO) RRAM. By using two terminals for writing and a third, dedicated decoupled terminal for reading, this architecture allows for simultaneous and asynchronous read and write operations. This approach resolves the read–write conflict inherent in 2-terminal designs, enabling real-time learning in SNNs without significant increase in circuit overhead and learning time.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112429"},"PeriodicalIF":3.1,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145622910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0