Microelectronic Engineering最新文献

{"title":"Ti and Ni-based BEOL CMOS-compatible P+-InGaAs ohmic contacts for the future of wireless communications","authors":"A. Lombrez ,&nbsp;H. Boutry ,&nbsp;A. Divay ,&nbsp;L. Colas ,&nbsp;N. Coudurier ,&nbsp;T. Baron","doi":"10.1016/j.mee.2025.112385","DOIUrl":"10.1016/j.mee.2025.112385","url":null,"abstract":"<div><div>We report the electrical results of scaled Ti and Ni-based P⁺-InGaAs (:C) ohmic contacts integrated with a CMOS-compatible flow on 200 mm Si substrates. To evaluate contact performance as well as thermal stability, Transfer Length Method (TLM) measurements were first conducted after rapid thermal annealing (RTA). The targeted temperatures are relevant to the typical Si-CMOS Back End Of Line (BEOL) thermal budgets. The issue of acceptor passivation, resulting from hydrogen exposure of the InGaAs layer during CMOS-compatible process, is then emphasized. The etching of the contact cavities was identified as being the root cause. Finally, a previously developed TLM-based numerical extraction method was employed to achieve a more precise assessment of the resistivity parameters. Specific contact resistivity values as low as 5 × 10⁻⁷ and 3 × 10⁻⁶ Ω*cm² were respectively extracted from scaled Ti-based and Ni-based contacts. The 5 × 10⁻⁷ Ω*cm² value approaches the required magnitude of 10⁻⁸ Ω*cm² for the base contact in a Heterojunction Bipolar Transistor (HBT) in order to reach THz performance, which is crucial for future 6G/sub-millimeter Wave (sub-mmW) applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"301 ","pages":"Article 112385"},"PeriodicalIF":2.6,"publicationDate":"2025-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144711861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quantitative assessment of adhesion strength in hybrid bonded interfaces with varying metal contact density","authors":"Kris Vanstreels,&nbsp;Oguzhan Orkut Okudur,&nbsp;Mario Gonzalez,&nbsp;Eric Beyne","doi":"10.1016/j.mee.2025.112384","DOIUrl":"10.1016/j.mee.2025.112384","url":null,"abstract":"<div><div>This work systematically investigates the influence of metal contact density and pitch size on the adhesion strength of hybrid bonded interfaces using an energy-based nanoindentation methodology to quantify interfacial bond strength. Results show that the presence of metal at the bonding interface enhances adhesion strength of hybrid bonded interfaces, with the effect becoming increasingly pronounced for lower pitch sizes. This enhancement is attributed to the role of metal/metal interfaces as crack-arresting sites during interfacial fracture. The findings in this work provide critical insights for optimizing hybrid bonding designs in advanced interconnect technologies.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112384"},"PeriodicalIF":2.6,"publicationDate":"2025-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144685999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Frequency-selective and high-performance wireless power transmission system for a multifunctional capsule endoscope: A feasibility study","authors":"Phi Cuong Ly ,&nbsp;Ngoc Thuy Thi Nguyen ,&nbsp;Tongil Park ,&nbsp;Hana Choi ,&nbsp;Doyeon Bang ,&nbsp;Jong-Oh Park ,&nbsp;Byungjeon Kang ,&nbsp;Kim Tien Nguyen ,&nbsp;Jayoung Kim","doi":"10.1016/j.mee.2025.112387","DOIUrl":"10.1016/j.mee.2025.112387","url":null,"abstract":"<div><div>Due to limitations in receiving power and controllability, wireless power transmission remains an open challenge for implantable devices and the active multifunctional capsule endoscope. This work introduces a novel high-performance resonant wireless power transmission system featuring selective operating frequency control. The system is comprised of a controllable transmitting unit and multiple receiving units. The transmitting unit is capable of generating powerful alternative magnetic field at multiple desired frequencies, while each of the receiving units is designed to resonate with the transmission signal at a desired frequency. This enabled selective wireless power delivery in our region of interest across a frequency range from 70 to 100 kHz, with maximum power transfer efficiency of 35 % measured at frequency of 100 kHz and distance 9 cm from transmission coil. Furthermore, this system demonstrated successful independent control of the temperature by heating coils for the morphology changes of each soft actuator, enabling the locomotion of the soft capsule endoscope.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"301 ","pages":"Article 112387"},"PeriodicalIF":3.1,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144723035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Potential of ultrahigh-vacuum based surface treatments in silicon technology","authors":"Z. Jahanshah Rad,&nbsp;M. Miettinen,&nbsp;R. Punkkinen,&nbsp;P. Suomalainen,&nbsp;M. Punkkinen,&nbsp;P. Laukkanen,&nbsp;K. Kokko","doi":"10.1016/j.mee.2025.112382","DOIUrl":"10.1016/j.mee.2025.112382","url":null,"abstract":"<div><div>Ultrahigh vacuum (UHV) environment with the background pressure in the range of 1‧10⁻¹⁵–1‧10⁻¹¹ bar is common in surface-science experiments, but UHV-based material treatments are rarely used in the current silicon technology. UHV methods might however provide a clear benefit to the technology when atomic-level cleanliness and crystalline order of Si surfaces (interfaces) as well as dry-cleaning methods for the surfaces become relevant to the development of Si devices. We have studied effects of some UHV-based treatments on the properties of Si surfaces and of thin oxide films on Si. Exposing Si, pre-cleaned by the RCA recipe with the final HF dip, to mere hydrogen (H₂) gas in UHV chamber at the Si temperature of 200 °C increases a crystalline degree of the Si surface according to low-energy electron diffraction. Effects of postheating in UHV are also studied for different oxidized Si surfaces. Wet chemically oxidized (RCA without HF dip) Si was heated step-by-step up to 800 °C in UHV until the oxide removal is strongly enhanced. Both crystalline degree of the RCA chemical oxide and surface roughness increase with the UHV post-heating at 500–800 °C. Exposing native-oxide covered sidewalls of Si diodes to mere oxygen (O₂) gas in UHV chamber at Si temperature of 350 °C (i) increases amount of SiO₂ at the sidewalls according to x-ray photoelectron spectroscopy, (ii) decreases amount of the band-gap electron levels at the sidewalls according to scanning tunneling spectroscopy, and (iii) provides a durable decrease in the diode leakage current.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112382"},"PeriodicalIF":2.6,"publicationDate":"2025-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144663052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A robust and efficient new paradigm for building in-memory stateful logic system with memristor: Based on multi-level co-optimization","authors":"Zhoujie Pan ,&nbsp;DingYi Zhang ,&nbsp;Yanming Liu ,&nbsp;He Tian","doi":"10.1016/j.mee.2025.112379","DOIUrl":"10.1016/j.mee.2025.112379","url":null,"abstract":"<div><div>This paper introduces a new paradigm of memristor-based in-memory stateful logic computing. Based on multi-level co-optimization. In device level, with the aid of Mirrored RRAM Device (MRD), we develop a scheme to build basic logics by a single device in a reconfigurable manner. Furthermore, we also proposed a method for cascading logic to construct more complex logic. Compared to existing architectures, our MRD based method exhibits robustness against voltage and device variations, and eliminates the need for multiple reference voltages. Our method also support execution of more complex logic operations, such as 1-bit full adders, through a cascaded configuration in just three steps using four MRD devices. SPICE simulations have been conducted to validate the feasibility of our approach. These advancements position the MRD as a promising candidate for scalable and efficient in-memory computing applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112379"},"PeriodicalIF":2.6,"publicationDate":"2025-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144653763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance enhancement of a spacer-engineered GS SOI n-FinFET with 10 nm gate length","authors":"Bhavya Kumar ,&nbsp;Anurag Somayajula ,&nbsp;Vishnu Sajith ,&nbsp;Tanish Aggarwal ,&nbsp;Rishu Chaujar","doi":"10.1016/j.mee.2025.112383","DOIUrl":"10.1016/j.mee.2025.112383","url":null,"abstract":"<div><div>This study showcases the improvement in conventional SOI n-FinFET devices with the incorporation of a high-K spacer and gate stack (GS) engineering at 10 nm gate length. Three FinFET configurations were considered for comparison, and the simulated results show significant improvements in the analog and RF performance of the proposed configuration. Analog parameters such as the I_ON/I_OFF ratio increased almost 10⁴ times, subthreshold swing reduced by ∼60 %; transconductance increased by ∼92 %, QF improved by ∼382 %, TGF enhanced by ∼302 %, intrinsic gain increased by almost 8 times, and early voltage by almost 5 times, indicating the proposed device is suitable for high-performance CMOS circuits. Further, the RF analysis is performed with parameters like cut-off frequency, GFP, TFP, etc., exhibiting considerable improvement for the proposed configuration. Thus, gate stacking and spacer engineering significantly improve the FinFET performance, enhancing the analog and RF capabilities of semiconductor devices for more efficient integrated circuits.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112383"},"PeriodicalIF":2.6,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144653875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Use of a hybrid metrology approach to develop holistic filtration solutions in hydrogen peroxide","authors":"Kusum Maharjan ,&nbsp;Nicole Williams ,&nbsp;Sally Huang ,&nbsp;Siddarth Sampath ,&nbsp;Briana Dufek ,&nbsp;Suhas Ketkar ,&nbsp;Austin Schultz","doi":"10.1016/j.mee.2025.112381","DOIUrl":"10.1016/j.mee.2025.112381","url":null,"abstract":"<div><div>All semiconductor manufacturers are driving to advance their process efficiency and effectiveness to deliver improved performance. To achieve such improvements with each generation of new semiconductor devices while maintaining high reliability and yield, strict contamination control must be established for process chemicals and gases. Contaminants in these materials can be present in various forms, such as organics, gels, solid particles, anions, cations, polymers, etc., and are typically controlled using membrane-based filtration. To ensure that the appropriate filtration solutions are implemented, a two-step process is required. First, one must identify/characterize the contaminants present in the semiconductor grade chemistry using multiple analytical techniques to develop a diverse profile of contaminants and then use that knowledge to optimize filtration schemes across the supply chain to ensure end-to-end impurity control. In this paper, a hybrid metrology approach was utilized to first understand the contamination profile of semiconductor grade hydrogen peroxide (H₂O₂) at 30 % concentration then evaluate the effectiveness of different filter membranes in removing these contaminants from the chemical.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112381"},"PeriodicalIF":2.6,"publicationDate":"2025-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144604603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Actinic defect inspection and characterization for extreme ultraviolet mask blanks","authors":"Hala Mohammad ,&nbsp;Bochao Li ,&nbsp;Jamilu Tijjani Baraya ,&nbsp;Zhenlong Zhao ,&nbsp;Xiaowei Song ,&nbsp;Jingquan Lin","doi":"10.1016/j.mee.2025.112378","DOIUrl":"10.1016/j.mee.2025.112378","url":null,"abstract":"<div><div>Extreme ultraviolet (EUV) lithography is crucial for advanced semiconductor manufacturing, relying on sophisticated mask technology to transfer intricate patterns onto silicon wafers. The integrity of the EUV mask blanks is essential for producing high-quality masks and semiconductor devices. However, defects in mask blanks, particularly multilayer phase defects, can significantly degrade lithographic quality, affecting device yield and performance. Actinic blank inspection (ABI) has emerged as the most effective strategy for evaluating the initial quality of EUV mask blanks and identifying defects that may compromise the wafer integrity. Additionally, defect characterization helps determine the nature of the defect, its printability, and its potential for repair. This review surveys recent advancements in ABI and defect characterization, covering a range of methodologies, commercial inspection tools and related research efforts that aimed at improving the detection and characterization of multilayer defects.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112378"},"PeriodicalIF":2.6,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144589063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced gallium nitride high electron mobility transistors for biosensing applications: Progress, challenges, and future perspectives","authors":"A. Revathy ,&nbsp;S. Ravi ,&nbsp;A. Lakshmi Narayana ,&nbsp;K. Nirmala Devi ,&nbsp;Raji Pandurangan","doi":"10.1016/j.mee.2025.112380","DOIUrl":"10.1016/j.mee.2025.112380","url":null,"abstract":"<div><div>GaN High Electron Mobility Transistors represent a breakthrough technology for biosensing applications, offering exceptional sensitivity through their unique two-dimensional electron gas channel positioned close to the sensing surface. This comprehensive review provides the first systematic analysis of the complete GaN HEMT biosensor ecosystem, distinguishing itself from previous reviews through: (i) Comprehensive coverage of emerging architectural innovations including novel heterostructures, dimensional variants, and advanced gate engineering approaches; (ii) Detailed analysis of MOS-HEMT configurations and their superior performance in physiological media; and (iii) Critical assessment of commercialization challenges and practical implementation strategies. The fundamental advantage of GaN HEMTs lies in their ability to detect minute charge variations from biomolecular interactions with detection limits reaching attomolar concentrations, enabled by the 2DEG channel's proximity (20–30 nm) to the sensing surface. The review systematically examines device architectures ranging from conventional AlGaN/GaN structures to advanced MOS-HEMT designs with dielectric layers that provide 2–3× sensitivity enhancement while improving stability in high ionic strength media. Novel heterostructures including InAlN/GaN systems and N-polar configurations offer up to 4× sensitivity improvements compared to conventional designs. Different gate engineering approaches are analyzed, encompassing dual-gate architectures for differential sensing, recessed designs for enhanced control, and extended-gate configurations for harsh environments.</div><div>This review uniquely addresses the critical interface between device physics and practical biosensing through comprehensive analysis of surface functionalization strategies, charge screening mitigation techniques, and biocompatibility considerations. Current limitations including signal drift (0.1–2.0 mV/h), selectivity challenges in complex biological matrices, and manufacturing reproducibility (5–15 % coefficient of variation) are critically evaluated alongside emerging solutions involving differential measurements, anti-fouling surface modifications, and machine learning algorithms. Future developments focus on transformative trends not comprehensively covered in previous reviews: self-powered sensors with integrated energy harvesting, multi-modal detection platforms combining optical and electrochemical sensing, IoT-connected monitoring networks for population-level healthcare, and expanding environmental monitoring applications. These advances position GaN HEMT biosensors as enabling technologies for next-generation healthcare diagnostics, environmental monitoring, and smart sensing ecosystems.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112380"},"PeriodicalIF":2.6,"publicationDate":"2025-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144614334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A review on structure and manufacturing optimization of LDMOS devices","authors":"Yixian Song ,&nbsp;Hao Cai ,&nbsp;Dawei Gao ,&nbsp;Kai Xu","doi":"10.1016/j.mee.2025.112377","DOIUrl":"10.1016/j.mee.2025.112377","url":null,"abstract":"<div><div>Bipolar-CMOS-DMOS (BCD) is the mainstream manufacturing technology for power management integrated circuits (PMIC), with laterally diffused metal-oxide semiconductor (LDMOS) devices serving as the core component. This review provides a comprehensive overview of LDMOS device structures, manufacturing processes, and applications. It discusses the fundamental structure and working principles, encompassing the manufacturing processes, critical technological features, and industry-specific module descriptions. Furthermore, it introduces device optimization strategies</div><div>tailored to various application scenarios. By integrating insights from both industry and academia, this review highlights emerging trends and challenges in the field, offering a forward-looking perspective on LDMOS advancements and future research directions.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112377"},"PeriodicalIF":2.6,"publicationDate":"2025-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144570788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}