Microelectronic Engineering最新文献_第2页

Resistive switching characteristics of ZnO/HfO2 RRAM using TiN/Ti electrode with a graphene interlayer 石墨烯中间层TiN/Ti电极制备ZnO/HfO2 RRAM的电阻开关特性

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-03-01 Epub Date: 2025-12-30 DOI: 10.1016/j.mee.2025.112443

So-Yeon Kwon, Woon-San Ko, Ki-Nam Kim, Jun-Ho Byun, Do-Yeon Lee, Hi-Deok Lee, Ga-Won Lee

{"title":"Resistive switching characteristics of ZnO/HfO2 RRAM using TiN/Ti electrode with a graphene interlayer","authors":"So-Yeon Kwon, Woon-San Ko, Ki-Nam Kim, Jun-Ho Byun, Do-Yeon Lee, Hi-Deok Lee, Ga-Won Lee","doi":"10.1016/j.mee.2025.112443","DOIUrl":"10.1016/j.mee.2025.112443","url":null,"abstract":"<div><div>In this study, the structure with a graphene interlayer in a ZnO/HfO<sub>2</sub> bilayer Resistive Random-Access Memory (RRAM) is proposed. Two types of devices were fabricated to compare the effect of graphene interlayer: one with a TiN/Ti/graphene Top Electrode (TE) device and another with a TiN/Ti TE device. The condition of the single-layer graphene was confirmed using Raman spectroscopy. The TiN/Ti/graphene TE device demonstrates an enhanced uniformity of both the set voltage (V<sub>set</sub>) and reset voltage (V<sub>reset</sub>). The window for the switching voltage decreases by 2.1 V, and the average on/off ratio increases by 20.09 times. The structure also exhibits self-compliance characteristics. These results highlight both the advantages of the graphene interlayer and the oxygen-scavenging properties of TiN/Ti TE. Detailed mechanisms of oxygen ion blocking by graphene interlayer are analyzed using the standard Gibbs free energy of formation (∆G<sub>f</sub>°). The switching characteristics are analyzed by the structure's work function. And the conduction mechanism is analyzed by the space-charge limited current (SCLC), related to traps.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112443"},"PeriodicalIF":3.1,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145884161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and characterization of 2-GaN MIS-HEMT integrated cascode power module 2-GaN miss - hemt集成级联码功率模块的设计与表征

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-03-01 Epub Date: 2025-12-31 DOI: 10.1016/j.mee.2025.112439

Surya Elangovan , Stone Cheng , Edward Yi Chang , Tejender Singh Rawat , Yi-Kai Hsiao , Chang-Ching Tu , Hao-Chung Kuo

{"title":"Design and characterization of 2-GaN MIS-HEMT integrated cascode power module","authors":"Surya Elangovan , Stone Cheng , Edward Yi Chang , Tejender Singh Rawat , Yi-Kai Hsiao , Chang-Ching Tu , Hao-Chung Kuo","doi":"10.1016/j.mee.2025.112439","DOIUrl":"10.1016/j.mee.2025.112439","url":null,"abstract":"<div><div>A cascode gallium nitride (GaN) switch integrating two paralleled GaN depletion-mode metal-insulator-semiconductor (MIS) high-electron-mobility transistors (HEMT) and a silicon MOSFET (Si-MOSFET) are presented. Each GaN chip is wire-bonded into a multi-chip power module to scale up the power rating. An optimized symmetric configuration and wire bonding of an integral package are used in the novel cascode switch. The developed GaN cascode switch was verified for validity through both static and dynamic characterizations in an optimized package. Static characterization reveals a significant reduction in RDS-ON from 282 mΩ (single MIS-HEMT) to 146 mΩ (dual-GaN cascode) with a threshold voltage shift to 4.2 V, confirming safe and reliable enhancement-mode operation. Dynamic switching performance, evaluated using double-pulse testing, demonstrates that the dual-GaN configuration maintains fast turn-on/off times with minimal increase relative to a single-GaN cascode. Voltage- and current-dependent measurements indicate a moderate increase in dynamic RDS-ON due to charge trapping and hot carrier injection, which stabilizes at higher voltages. These results highlight the feasibility of paralleling GaN HEMTs in a cascode configuration to enhance performance, reliability, and scalability in high-power applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112439"},"PeriodicalIF":3.1,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145925220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A DC − 24 GHz SPDT switch design in 22 nm FD-SOI CMOS for 5G FR1 and FR3 bands 基于22 nm FD-SOI CMOS的5G FR1和FR3频段DC - 24 GHz SPDT开关设计

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-03-01 Epub Date: 2025-11-29 DOI: 10.1016/j.mee.2025.112428

F. Silva , L.-W. Ouyang , D.Y.C. Lie , C. Sweeney , J. Lopez

{"title":"A DC − 24 GHz SPDT switch design in 22 nm FD-SOI CMOS for 5G FR1 and FR3 bands","authors":"F. Silva , L.-W. Ouyang , D.Y.C. Lie , C. Sweeney , J. Lopez","doi":"10.1016/j.mee.2025.112428","DOIUrl":"10.1016/j.mee.2025.112428","url":null,"abstract":"<div><div>A fully-monolithic DC - 24 GHz SPDT (single-pole-double-throw) RF (radio-frequency) switch IC (integrated circuit) is designed and taped out in a 22 nm FD-SOI (fully-depleted silicon-on-insulator) CMOS process, targeting 5G FR1 and FR3 band applications. The first-generation switch (SW1) has measured insertion loss of about 1.9/2.8/3.8 dB at 10/18/24 GHz, reasonably close to the simulation data within 0.5 dB, and measured receive-antenna (RX-ANT) isolation of around 28.2/23.2/20.7 dB at 10/18/24 GHz. However, we found both the post-layout parasitic (PEX) RCC simulations (accounting for resistance, capacitance, and coupling capacitance) and the EM (electromagnetic) simulations underestimated the switch's insertion loss compared with measurement data, especially at frequencies above 30 GHz. To reduce this loss and to design a switch that may operate at the higher frequency FR2 band (i.e., 24.25–52.6 GHz), a second-generation switch (SW2) with improved transistor sizing and a matching network is proposed. PEX-RCC simulations indicate that the SW2 may reduce the insertion loss by up to ∼1 dB at 24 GHz vs. SW1, while maintaining the TX-RX isolation above 30 dB.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112428"},"PeriodicalIF":3.1,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145623075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Evaluation of the robustness of the defect-centric model for defect parameter extraction from RTN and BTI analysis using Comphy 缺陷中心模型在RTN和BTI分析中缺陷参数提取的鲁棒性评价

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-03-01 Epub Date: 2025-12-05 DOI: 10.1016/j.mee.2025.112436

Martin E.M. Loesener , Tobias Zinsler , Bernhard Stampfer , Florian Wimmer , Eleftherios Ioannidis , Walter Pflanzl , Rainer Minixhofer , Tibor Grasser , Michael Waltl

{"title":"Evaluation of the robustness of the defect-centric model for defect parameter extraction from RTN and BTI analysis using Comphy","authors":"Martin E.M. Loesener , Tobias Zinsler , Bernhard Stampfer , Florian Wimmer , Eleftherios Ioannidis , Walter Pflanzl , Rainer Minixhofer , Tibor Grasser , Michael Waltl","doi":"10.1016/j.mee.2025.112436","DOIUrl":"10.1016/j.mee.2025.112436","url":null,"abstract":"<div><div>Advanced reliability simulators like Comphy capture much of the state-of-the-art modeling behind charge trapping processes. An alternative approach to Comphy is to apply stochastic models, e.g. the defect-centric model, directly to the experimental data to extract the impact of defects on the device behavior and trap densities. In order to efficiently design defect characterization experiments, however, it is of utmost importance to understand the robustness of the defect-centric model under a variety of pre-conditions. In this work, we evaluate the requirements to employ the defect-centric model for data analysis, using simulated data from Comphy based on a real 400 nm × 180 nm pMOS device. Our results show that the number of devices from wafer-level tests does not suffice for statistical evaluation of RTN analysis. Here, preferably array chips should be used. For BTI studies, both wafer-level and array-chip tests enable us to extract good estimates for defect parameters with little computational effort.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"303 ","pages":"Article 112436"},"PeriodicalIF":3.1,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145692374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance enhancement of InSnZnO thin-film transistors by dual-active-layer architecture with various oxygen flow rates 不同氧流量下双有源层结构对InSnZnO薄膜晶体管性能的增强

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-01-11 Epub Date: 2025-09-09 DOI: 10.1016/j.mee.2025.112403

Jinbao Su , Yaobin Ma , Yihong Liu , Yiyang Xie

{"title":"Performance enhancement of InSnZnO thin-film transistors by dual-active-layer architecture with various oxygen flow rates","authors":"Jinbao Su , Yaobin Ma , Yihong Liu , Yiyang Xie","doi":"10.1016/j.mee.2025.112403","DOIUrl":"10.1016/j.mee.2025.112403","url":null,"abstract":"<div><div>Oxide thin film transistors (TFTs) have been one of the promising transistors in high-resolution displays. Unfortunately, their electrical performance, especially mobility, is limited by oxygen related defects in the active layers. Here, a homojunction dual-active-layer architecture using sputtering oxygen strategy is employed to enhance the electrical performance of InSnZnO (ITZO) TFTs. The ITZO dual active layers with varying oxygen contents are sequentially sputtered by adjusting the oxygen gas flow rate. The oxygen effects on the electrical performance of the ITZO TFTs are investigated. As the oxygen content increases, the mobility decreases while the threshold voltage increases. The dual-active-layer architecture, composed of ITZO films with varying oxygen contents, significantly improves the mobility. The dual-layer ITZO TFT shows excellent performance with a mobility of 50.51 ± 4.16 cm<sup>2</sup>/V·s, a subthreshold swing of 0.59 ± 0.19 V/dec, a threshold voltage of −0.77 ± 1.40 V, an off-state current of ∼10<sup>−12</sup> A, and an on/off-state current ratio of more than 10<sup>8</sup>. The gate bias stress stability of the ITZO TFTs is investigated. Under negative bias stress, the threshold voltage shift in single-layer TFTs improves from −14 to −8 V as the oxygen flow rate increases from 1 to 7 SCCM. The dual-layer TFTs show a reasonable threshold voltage shift under bias stress. This work demonstrates that the ITZO TFTs exhibit great potential for next-generation electronic applications.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112403"},"PeriodicalIF":3.1,"publicationDate":"2026-01-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145020741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Process development and integration of hybrid bonding for wafers with multi-type bonding pads 多类型键合片混合键合的工艺开发与集成

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-01-11 Epub Date: 2025-10-13 DOI: 10.1016/j.mee.2025.112420

Guoqiang Zhao , Yi Zhao

引用次数: 0

Extensive FPGA and ASIC resource comparison for blind I/Q imbalance estimators and compensators 广泛的FPGA和ASIC资源比较盲I/Q不平衡估计器和补偿器

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-01-11 Epub Date: 2025-11-03 DOI: 10.1016/j.mee.2025.112421

Moritz Tockner , Moritz Stockinger , Oliver Lang , Andreas Meingassner , Mario Huemer

{"title":"Extensive FPGA and ASIC resource comparison for blind I/Q imbalance estimators and compensators","authors":"Moritz Tockner , Moritz Stockinger , Oliver Lang , Andreas Meingassner , Mario Huemer","doi":"10.1016/j.mee.2025.112421","DOIUrl":"10.1016/j.mee.2025.112421","url":null,"abstract":"<div><div>In wireless communications, in-phase (I) and quadrature-phase (Q) imbalance is a well-understood issue, and an extensive body of different I/Q imbalance estimation and compensation algorithms exists in the literature. Many of these algorithms, including those in this work, focus on mitigating I/Q imbalance on the receiver side. We consider frequency-independent (FID) estimators that operate as so-called blind algorithms, where little to no knowledge about the transmitted data is required. However, little effort has been made to compare the required resources for implementing these algorithms in hardware. In this work, we compare a comprehensive list of such algorithms with regard to their logic utilization, required registers, and embedded multipliers when implementing them on a field-programmable gate array (FPGA). Subsequently, we provide synthesis results based on the SkyWater 130nm open-source process design kit (PDK), which enables comparisons of the required chip areas for the corresponding application-specific integrated circuit (ASIC) designs. We optimize the fixed-point bit-widths, and other hardware implementation specific parameters of the individual estimators to provide meaningful results. This optimization aims to achieve a common performance target for a typical orthogonal frequency-division multiplexing (OFDM) signal scenario.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112421"},"PeriodicalIF":3.1,"publicationDate":"2026-01-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145465427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Simulation of SAF-enhanced multilayered STT-MRAM structures saf增强多层STT-MRAM结构的仿真

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-01-11 Epub Date: 2025-11-06 DOI: 10.1016/j.mee.2025.112426

M. Bendra , W. Goes , S. Selberherr , V. Sverdlov

{"title":"Simulation of SAF-enhanced multilayered STT-MRAM structures","authors":"M. Bendra , W. Goes , S. Selberherr , V. Sverdlov","doi":"10.1016/j.mee.2025.112426","DOIUrl":"10.1016/j.mee.2025.112426","url":null,"abstract":"<div><div>The reliability of multilayered spin-transfer torque magnetoresistive random access memory with synthetic antiferromagnets is crucial for computing-in-memory architectures, high-performance computing, and high-density storage applications. This study investigates the role of interlayer exchange coupling in magnetic tunnel junction structures, which are fundamental to spin-transfer torque magnetoresistive random access memory performance and stability. We analyze how interlayer exchange coupling influences magnetic stability and spin-transfer torque switching efficiency using finite element method simulations combined with the Landau–Lifshitz–Gilbert equation. Our findings reveal that optimizing interlayer exchange coupling not only enhances data retention and write/read speeds but also mitigates miniaturization challenges and improves device reliability in downscaled spin-transfer torque magnetoresistive random access memory technologies. The results further emphasize the strong dependence of interlayer exchange coupling on spacer properties, which dictate magnetic orientations and coupling energy, offering a strategic pathway to engineer more efficient and robust spin-transfer torque magnetoresistive random access memory devices. This work highlights the critical impact of magnetic coupling on the switching dynamics and long-term stability of spintronic memory, providing insights that pave the way for next-generation, high-performance memory solutions.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112426"},"PeriodicalIF":3.1,"publicationDate":"2026-01-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145465428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Understanding the impact of contacts and top gate scaling on the reliability of nanoscale MoS2 FETs by TCAD modeling 通过TCAD建模了解触点和顶栅极缩放对纳米MoS2 fet可靠性的影响

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-01-11 Epub Date: 2025-11-03 DOI: 10.1016/j.mee.2025.112425

Yezhu Lv, Yajing Chai, Yehao Wu, Yury Yu. Illarionov

{"title":"Understanding the impact of contacts and top gate scaling on the reliability of nanoscale MoS2 FETs by TCAD modeling","authors":"Yezhu Lv, Yajing Chai, Yehao Wu, Yury Yu. Illarionov","doi":"10.1016/j.mee.2025.112425","DOIUrl":"10.1016/j.mee.2025.112425","url":null,"abstract":"<div><div>Localized defects in the edges of top gate insulators present a serious obstacle for scaling of field-effect transistors (FETs) with 2D channels. However, most experimental studies of their bias stability are performed on micron-scale prototypes. In these devices homogeneous trap distributions can be assumed since the edges are negligible as compared to the channel lengths, and thus their bias stability is mostly determined by the energy barrier between the oxide defect bands and the conduction band edge of the channel (for n-FETs). By doing technology computer aided design (TCAD) modeling for nanoscale MoS<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span>/HfO<span><math><msub><mrow></mrow><mrow><mn>2</mn></mrow></msub></math></span> FETs with edge trap distributions, here we for the first time demonstrate that the hysteresis and positive bias-temperature instabilities (PBTI) may strongly depend on the Fermi level pinning, type of S/D contact and top gate scaling. As a result, even favorable alignment of oxide defect bands with respect to the channel conduction band edge may result in poor bias stability and vice versa. With these findings we open a pathway towards reliability-aware design of scalable 2D electronics which is currently disregarded by the industry.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"302 ","pages":"Article 112425"},"PeriodicalIF":3.1,"publicationDate":"2026-01-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145465429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A statistical characterization of dielectric breakdown in FDSOI nanowire transistors FDSOI纳米线晶体管中介电击穿的统计特性

IF 3.1 4区工程技术

Microelectronic Engineering Pub Date : 2026-01-11 Epub Date: 2025-10-06 DOI: 10.1016/j.mee.2025.112422

R. Goyal, A. Crespo-Yepes, M. Porti, R. Rodriguez, M. Nafria

引用次数: 0