Microelectronic Engineering最新文献

{"title":"On the feature accuracy of deep learning mask topography effect models","authors":"Linus Engelmann ,&nbsp;IrenaeusWlokas","doi":"10.1016/j.mee.2025.112332","DOIUrl":"10.1016/j.mee.2025.112332","url":null,"abstract":"<div><div>A deep-learning-based lithography model using a generative neural network (GAN) approach is developed and assessed for its ability to predict aerial images at different resist heights. The performance of the GAN approach is evaluated by analyzing deviations between model-generated aerial images and golden images, as well as differences in critical dimension (CD) values. Additionally, error analysis is conducted based on the feature distribution of each photomask. Selected patterns and their aerial images are compared both qualitatively to assess local errors and quantitatively through root-mean-square (RMS) errors to evaluate global accuracy. Error analysis reveals the features produced by the deep learning model leading to the highest deviation from the rigorous model results, and the error is decomposed into the error contributions of underpredicted and overpredicted features. An array of aerial images for selected resist heights produced by the deep learning model is assessed, revealing increasing errors with increasing resist heights. The limitations of applying deep learning techniques in computational lithography are illustrated by comparing a target pattern with and without optical proximity correction (OPC) features.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112332"},"PeriodicalIF":2.6,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143529001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of constant bias stress on reliability of IGZO thin-film transistors on softening polymer","authors":"Gerardo Gutierrez-Heredia ,&nbsp;Ovidio Rodriguez-Lopez ,&nbsp;Pedro Emanuel Rocha-Flores ,&nbsp;Walter E. Voit","doi":"10.1016/j.mee.2025.112331","DOIUrl":"10.1016/j.mee.2025.112331","url":null,"abstract":"<div><div>This study analyzed the electrical behavior of indium‑gallium‑zinc-oxide (IGZO) thin-film transistors (TFTs) under different applied voltages. The IGZO TFTs were fabricated on a polymer substrate using full photolithographic processes. The electrical performance was monitored under constant bias stress for 10,000 s and the analysis revealed relatively high field-effect mobility (&gt;10 cm²/Vs) when higher voltages (&gt;5 V) were applied to the IGZO TFTs. Furthermore, the experimental results demonstrated shifts in the threshold voltage (V_TH), mobility, and saturation drain current, exhibiting a strong dependence on the applied voltage. After 10,000 s of bias stress, the threshold voltage shift varied by 0.5 V for the lowest applied voltage and exceeded 5 V for the higher values. Moreover, the electrical analysis indicated a significant reduction in the lifetime of IGZO TFTs when the applied voltage exceeded 15 V. These findings enable a comparative analysis of the impact of bias stress on mobility, V_TH, and driving current, offering a pathway to optimize the electrical performance of TFTs-based flexible applications. Furthermore, by exploring the mechanism behind the changes induced by the constant electric field at the gate contact, this work provides insights for predicting the reliability and lifetime of novel devices tailored for wearable, flexible, and biomedical technologies.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112331"},"PeriodicalIF":2.6,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143512523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal management of through-silicon vias and back-end-of-line layers in 3D ICs: A comprehensive review","authors":"Hongbang Zhang ,&nbsp;Miao Tian ,&nbsp;Xiaokun Gu","doi":"10.1016/j.mee.2025.112325","DOIUrl":"10.1016/j.mee.2025.112325","url":null,"abstract":"<div><div>Three-dimensional integrated circuits (3D ICs) have emerged at the forefront of semiconductor research due to their potential for enhancing performance and reducing power consumption. As semiconductor technology advances, the continuous miniaturization and increasing integration density of 3D ICs have made size and interface effects more pronounced, leading to higher heat flux densities and more complex thermal management challenges. Through‑silicon via (TSV) and back-end-of-line (BEOL) structures, as core components of 3D ICs, are responsible for horizontal and vertical interconnections and directly affect the thermal transport performance within the chip. In this review, we provide an overview of the current state of thermal management in TSVs and BEOL structures, discussing heat dissipation performance, thermal parameter extraction, structural optimization, and the development of layout algorithms. In response to the challenges of cross-scale simulations and the difficulty of characterizing the thermal properties and temperature distribution of complex micro-nano scale structures, the current state of theoretical calculations and thermal testing techniques at the micro-nano scale, which have been evolved as powerful tools in thermal management of 3D ICs, is also presented. This review summarizes the key advances and challenges in this field, highlighting the importance of addressing these issues to optimize TSVs and BEOL designs and enhance the thermal management performance of 3D ICs, providing valuable reference and guidance for future research.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112325"},"PeriodicalIF":2.6,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143474091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of read operation for low power consumption in 3D NAND flash memory","authors":"Jesun Park ,&nbsp;Seongwoo Kim ,&nbsp;Taeyoung Cho ,&nbsp;Myounggon Kang","doi":"10.1016/j.mee.2025.112324","DOIUrl":"10.1016/j.mee.2025.112324","url":null,"abstract":"<div><div>This study proposes a low power read operation to minimize the hot carrier injection (HCI) phenomenon that occurs during read operations in 3D NAND Flash Memory. Owing to the characteristics of the 3D NAND Flash Memory structure, the channels of unselected strings can easily remain in a floating state. This leads to HCI during read operations, resulting in read disturbances. To improve the read disturb characteristics, triangular pulse voltages (V_TP) with adjusted slopes and delayed application times were applied to the string selected line (SSL) and the ground selected line (GSL) during read operations. Using the proposed read scheme, it was confirmed that HCI was decreased compared to the conventional method, and it was possible to operate at low power.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112324"},"PeriodicalIF":2.6,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143474092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of edge bead removal (EBR) process to enhance defect reduction in optical lithography","authors":"Bishnu P. Khanal,&nbsp;Marlene Dugger","doi":"10.1016/j.mee.2025.112330","DOIUrl":"10.1016/j.mee.2025.112330","url":null,"abstract":"<div><div>Defect reduction remains a critical objective in the integrated circuit manufacturing process, particularly within the highly re-entrant lithography modules where minimizing defects is crucial. Defects at the wafer edge can contaminate lithography modules and downstream processing equipment, leading to redistribution onto the wafer surface and adversely affecting overall device yield. A persistent challenge in the resist coating process is the formation of resist edge beads, driven by the strong Van der Waals attraction of excess photoresist (PR) to itself and the underlying substrate. The edge bead removal (EBR) process is a standard cleaning step designed to eliminate these edge beads and prevent potential contamination.</div><div>In this study, we identify the sources of EBR induced defects and additional EBR process encroachment toward edge patterning during the EBR cleaning process. This study provides a comprehensive study aimed at optimizing the EBR cleaning process to effectively eliminate EBR-induced defects, thereby enhancing overall device yield. Specifically, we identify three primary defects induced by the EBR cleaning process: rainbow-type, finger-shaped, and teardrop-type defects. Our experimental study reveals that in addition to EBR rinse time, PR cast time is crucial parameters contributing to the formation of these defects. By properly optimizing the PR cast time and EBR rinse time, we were able to remove nearly 100 % of dense clusters of defects that were easily visible even at low magnification optical microscopy throughout the wafer edge. We observed that shorter PR casting times shows edge defects caused by inefficient EBR process because of insufficient time for PR to fully settle causing superfluous PR to continue flowing toward wafer edge during EBR clearing step, leading to partial removal of PR at the wafer edge and the formation of rainbow defects. Proper optimization of both PR casting time and EBR chemistries dispense time is essential to resolve these defects, ensuring efficient EBR cleaning process and improved overall device yield.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112330"},"PeriodicalIF":2.6,"publicationDate":"2025-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143444796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Neural network for in-sensor time series recognition based on optoelectronic memristor","authors":"Zhang Zhang ,&nbsp;Qifan Wang ,&nbsp;Gang Shi ,&nbsp;Gang Liu","doi":"10.1016/j.mee.2025.112329","DOIUrl":"10.1016/j.mee.2025.112329","url":null,"abstract":"<div><div>In recent years, inspired by multifunctional image sensors, in-sensor computing technology that combines sensing and computing functions has become a new research hotspot in the field of machine vision, which is an extremely promising way to break through the Von Neumann architecture by equipping the sensing unit with the computing ability and avoiding the data moving in the computation process. Whereas most existing in-sensor computing systems can only realize the processing of spatial frames in-sensor and cannot fuse the time series information. In order to solve this limitation and realize the processing of time information and spatial frames in the sensor at the same time, it is necessary to decouple and process the information in the processing unit in the sensor. In this paper, a time series recognition neural network based on optoelectronic memristor arrays is proposed. By using the optical plasticity and relaxation effects of the optoelectronic memristor arrays and based on the in-sensor computing technology, the information timing decoupling, processing and recognition in the sensor are realized. The results show that the network achieves a time series recognition accuracy of 98.4 % with two frames of image input, and the recognition rate still reaches 90 % after weight quantization and the addition of 40 % noise.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112329"},"PeriodicalIF":2.6,"publicationDate":"2025-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143464427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of pattern quality in DMD scanning maskless lithography: A parametric study of the OS3L exposure algorithm","authors":"Ting-Hsuan Miau ,&nbsp;Yung-Chun Lee","doi":"10.1016/j.mee.2025.112328","DOIUrl":"10.1016/j.mee.2025.112328","url":null,"abstract":"<div><div>In digital micromirror device (DMD) scanning maskless lithography systems, the pattern accuracy has a critical effect on the final component quality. However, the patterning performance is highly sensitive to the parameters used in the scanning process. Accordingly, this study examines the effects of three key parameters (the rotation angle of the DMD array, the step size, and the optical distortion of the image projection lens) on the patterning quality of a DMD-based scanning maskless lithography system utilizing an oblique scanning and step-strobe lighting (OS³L) exposure algorithm. The MATLAB simulation results show that the optical distortion of the image projection lens causes an uneven distribution of the exposure points along the <em>x</em>-axis direction, with sparser focal spots on the sides of the exposure field and denser spots in the center. In addition, the results suggest that the DMD rotation angle should be close to (but not less than) the critical angle, i.e., the angle at which the maximum horizontal resolution is obtained. Finally, the light spot distribution is extremely sensitive to the step size, but the relationship between them is unpredictable and nonlinear. Consequently, the effects of the step size on the light spot distribution should be checked on a case-by-case basis. Overall, the results presented in this study provide useful guidelines for the selection of the parameter settings that optimize the patterning quality in DMD-based scanning maskless lithography systems using the OS³L exposure algorithm.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112328"},"PeriodicalIF":2.6,"publicationDate":"2025-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143436478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Amorphous indium gallium zinc oxide thin film transistors (a-IGZO-TFTs): Exciting prospects and fabrication challenges","authors":"J. Ajayan ,&nbsp;S. Sreejith ,&nbsp;N. Aruna Kumari ,&nbsp;M. Manikandan ,&nbsp;Sachidananda Sen ,&nbsp;Maneesh Kumar","doi":"10.1016/j.mee.2025.112327","DOIUrl":"10.1016/j.mee.2025.112327","url":null,"abstract":"<div><div>In today's consumer electronics market, major manufacturing companies may be profitable and scalable thanks to technologies like thin-film transistors (TFTs). TFTs are found in TVs, smartphones, laptops, brain-like synaptic transistors, back-planes in CMOS image sensors, integrated circuits (ICs), flexible &amp; wearable electronics, power switching circuits, back-end-of-line (BEOL) transistor elements in 3D-logic and cell transistors in dynamic random-access memory (DRAM). They have also been proposed as a potential solution for flexible CPUs. A high mobility of 74.4 cm²/Vs and I_ON/I_OFF of 3.39 × 10⁹ and a V_ON of less than ±0.1 V and a SS of less than 0.1 V/dec were achieved in a-IGZO based TFTs. Numerous efforts have been made to enhance the a-IGZO TFTs' electrical characteristics by optimizing the fabrication process. Numerous studies have also addressed the instability problems, such as the a-IGZO devices' hot-carrier effects, self-heating, and charge-trapping. TFTs with a-IGZO are being extensively studied adopting the a vertical-channel approach in order to be used in 3-D electronic devices. This article reviews the recent developments in materials and architectures, performance overview of IGZO-TFTs, advances and challenges in fabrication technologies and reliability issues &amp; degradation mechanisms of IGZO-TFTs.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112327"},"PeriodicalIF":2.6,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143372220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Spin coating in semiconductor lithography: Advances in modeling and future prospects","authors":"Pan Liu ,&nbsp;Liejie Huang ,&nbsp;Chaoyi Zheng ,&nbsp;Yanan Bao ,&nbsp;Dawei Gao ,&nbsp;Guodong Zhou","doi":"10.1016/j.mee.2025.112326","DOIUrl":"10.1016/j.mee.2025.112326","url":null,"abstract":"<div><div>With the development of advanced integrated circuit technologies, semiconductor manufacturing processes have become increasingly important. Photolithography is one of the most critical and costly steps in chip manufacturing, and the quality of the photoresist film formed during the subprocess of spin-coating significantly impacts photolithography performance. The thickness of photoresist films ranges from several hundred nanometers to tens of micrometers, with uniformity requirements typically within ±1 %. These stringent specifications pose significant challenges to the stability and precision of the spin coating process. This review outlines the research progress on spin-coating and discusses various model-building methods, including theoretical analysis, experimentation, simulation, and machine learning. The paper highlights new experimental approaches and recent advancements aimed at optimizing the spin-coating process under different conditions.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112326"},"PeriodicalIF":2.6,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143314795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimized fabrication of subwavelength slanted gratings via laser interference lithography and faraday cage-assisted etching","authors":"Zhiyuan Jiang,&nbsp;Xingzhi Zhang,&nbsp;Wei He,&nbsp;Kai Jiang,&nbsp;Liang Wang","doi":"10.1016/j.mee.2025.112323","DOIUrl":"10.1016/j.mee.2025.112323","url":null,"abstract":"<div><div>Subwavelength slanted gratings are crucial components in devices such as augmented reality systems and optoelectronic sensors due to their high diffraction efficiency and compact design. However, their fabrication is often hindered by high costs and limited structural control. This paper presents a novel fabrication method that combines a laser interference lithography (LIL) process, optimized using a two-dimensional lithography simulation model, with a Faraday cage-assisted reactive ion etching (RIE) process. The simulation model integrates exposure intensity analysis under the standing wave effect with photoresist contrast curve characteristics, enabling accurate simulation of photoresist patterns and providing precise feedback on exposure time and the angle between exposure light beams to achieve precise control of key parameters, such as period and duty cycle. Compared to traditional models, it reduces complexity while delivering high accuracy. The LIL process optimized by this model achieves negligible period error and a duty cycle error <span><math><mo>≤</mo><mn>0.01</mn></math></span>. Faraday cage-assisted RIE further enhances control over grating height and tilt angle, achieving near-zero deviations. This scalable and cost-effective method provides a reliable solution for fabricating high-precision subwavelength slanted gratings, advancing their practical applications in sophisticated optical systems.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112323"},"PeriodicalIF":2.6,"publicationDate":"2025-01-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}