Microelectronic Engineering最新文献_第2页

Neural network for in-sensor time series recognition based on optoelectronic memristor

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-02-17 DOI: 10.1016/j.mee.2025.112329

Zhang Zhang , Qifan Wang , Gang Shi , Gang Liu

{"title":"Neural network for in-sensor time series recognition based on optoelectronic memristor","authors":"Zhang Zhang , Qifan Wang , Gang Shi , Gang Liu","doi":"10.1016/j.mee.2025.112329","DOIUrl":"10.1016/j.mee.2025.112329","url":null,"abstract":"<div><div>In recent years, inspired by multifunctional image sensors, in-sensor computing technology that combines sensing and computing functions has become a new research hotspot in the field of machine vision, which is an extremely promising way to break through the Von Neumann architecture by equipping the sensing unit with the computing ability and avoiding the data moving in the computation process. Whereas most existing in-sensor computing systems can only realize the processing of spatial frames in-sensor and cannot fuse the time series information. In order to solve this limitation and realize the processing of time information and spatial frames in the sensor at the same time, it is necessary to decouple and process the information in the processing unit in the sensor. In this paper, a time series recognition neural network based on optoelectronic memristor arrays is proposed. By using the optical plasticity and relaxation effects of the optoelectronic memristor arrays and based on the in-sensor computing technology, the information timing decoupling, processing and recognition in the sensor are realized. The results show that the network achieves a time series recognition accuracy of 98.4 % with two frames of image input, and the recognition rate still reaches 90 % after weight quantization and the addition of 40 % noise.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112329"},"PeriodicalIF":2.6,"publicationDate":"2025-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143464427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimization of pattern quality in DMD scanning maskless lithography: A parametric study of the OS3L exposure algorithm

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-02-14 DOI: 10.1016/j.mee.2025.112328

Ting-Hsuan Miau , Yung-Chun Lee

{"title":"Optimization of pattern quality in DMD scanning maskless lithography: A parametric study of the OS3L exposure algorithm","authors":"Ting-Hsuan Miau , Yung-Chun Lee","doi":"10.1016/j.mee.2025.112328","DOIUrl":"10.1016/j.mee.2025.112328","url":null,"abstract":"<div><div>In digital micromirror device (DMD) scanning maskless lithography systems, the pattern accuracy has a critical effect on the final component quality. However, the patterning performance is highly sensitive to the parameters used in the scanning process. Accordingly, this study examines the effects of three key parameters (the rotation angle of the DMD array, the step size, and the optical distortion of the image projection lens) on the patterning quality of a DMD-based scanning maskless lithography system utilizing an oblique scanning and step-strobe lighting (OS<sup>3</sup>L) exposure algorithm. The MATLAB simulation results show that the optical distortion of the image projection lens causes an uneven distribution of the exposure points along the <em>x</em>-axis direction, with sparser focal spots on the sides of the exposure field and denser spots in the center. In addition, the results suggest that the DMD rotation angle should be close to (but not less than) the critical angle, i.e., the angle at which the maximum horizontal resolution is obtained. Finally, the light spot distribution is extremely sensitive to the step size, but the relationship between them is unpredictable and nonlinear. Consequently, the effects of the step size on the light spot distribution should be checked on a case-by-case basis. Overall, the results presented in this study provide useful guidelines for the selection of the parameter settings that optimize the patterning quality in DMD-based scanning maskless lithography systems using the OS<sup>3</sup>L exposure algorithm.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112328"},"PeriodicalIF":2.6,"publicationDate":"2025-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143436478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Amorphous indium gallium zinc oxide thin film transistors (a-IGZO-TFTs): Exciting prospects and fabrication challenges

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-02-08 DOI: 10.1016/j.mee.2025.112327

J. Ajayan , S. Sreejith , N. Aruna Kumari , M. Manikandan , Sachidananda Sen , Maneesh Kumar

{"title":"Amorphous indium gallium zinc oxide thin film transistors (a-IGZO-TFTs): Exciting prospects and fabrication challenges","authors":"J. Ajayan , S. Sreejith , N. Aruna Kumari , M. Manikandan , Sachidananda Sen , Maneesh Kumar","doi":"10.1016/j.mee.2025.112327","DOIUrl":"10.1016/j.mee.2025.112327","url":null,"abstract":"<div><div>In today's consumer electronics market, major manufacturing companies may be profitable and scalable thanks to technologies like thin-film transistors (TFTs). TFTs are found in TVs, smartphones, laptops, brain-like synaptic transistors, back-planes in CMOS image sensors, integrated circuits (ICs), flexible & wearable electronics, power switching circuits, back-end-of-line (BEOL) transistor elements in 3D-logic and cell transistors in dynamic random-access memory (DRAM). They have also been proposed as a potential solution for flexible CPUs. A high mobility of 74.4 cm<sup>2</sup>/Vs and I<sub>ON</sub>/I<sub>OFF</sub> of 3.39 × 10<sup>9</sup> and a V<sub>ON</sub> of less than ±0.1 V and a SS of less than 0.1 V/dec were achieved in a-IGZO based TFTs. Numerous efforts have been made to enhance the a-IGZO TFTs' electrical characteristics by optimizing the fabrication process. Numerous studies have also addressed the instability problems, such as the a-IGZO devices' hot-carrier effects, self-heating, and charge-trapping. TFTs with a-IGZO are being extensively studied adopting the a vertical-channel approach in order to be used in 3-D electronic devices. This article reviews the recent developments in materials and architectures, performance overview of IGZO-TFTs, advances and challenges in fabrication technologies and reliability issues & degradation mechanisms of IGZO-TFTs.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112327"},"PeriodicalIF":2.6,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143372220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Spin coating in semiconductor lithography: Advances in modeling and future prospects

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-02-07 DOI: 10.1016/j.mee.2025.112326

Pan Liu , Liejie Huang , Chaoyi Zheng , Yanan Bao , Dawei Gao , Guodong Zhou

引用次数: 0

Optimized fabrication of subwavelength slanted gratings via laser interference lithography and faraday cage-assisted etching

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-01-26 DOI: 10.1016/j.mee.2025.112323

Zhiyuan Jiang, Xingzhi Zhang, Wei He, Kai Jiang, Liang Wang

{"title":"Optimized fabrication of subwavelength slanted gratings via laser interference lithography and faraday cage-assisted etching","authors":"Zhiyuan Jiang, Xingzhi Zhang, Wei He, Kai Jiang, Liang Wang","doi":"10.1016/j.mee.2025.112323","DOIUrl":"10.1016/j.mee.2025.112323","url":null,"abstract":"<div><div>Subwavelength slanted gratings are crucial components in devices such as augmented reality systems and optoelectronic sensors due to their high diffraction efficiency and compact design. However, their fabrication is often hindered by high costs and limited structural control. This paper presents a novel fabrication method that combines a laser interference lithography (LIL) process, optimized using a two-dimensional lithography simulation model, with a Faraday cage-assisted reactive ion etching (RIE) process. The simulation model integrates exposure intensity analysis under the standing wave effect with photoresist contrast curve characteristics, enabling accurate simulation of photoresist patterns and providing precise feedback on exposure time and the angle between exposure light beams to achieve precise control of key parameters, such as period and duty cycle. Compared to traditional models, it reduces complexity while delivering high accuracy. The LIL process optimized by this model achieves negligible period error and a duty cycle error <span><math><mo>≤</mo><mn>0.01</mn></math></span>. Faraday cage-assisted RIE further enhances control over grating height and tilt angle, achieving near-zero deviations. This scalable and cost-effective method provides a reliable solution for fabricating high-precision subwavelength slanted gratings, advancing their practical applications in sophisticated optical systems.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112323"},"PeriodicalIF":2.6,"publicationDate":"2025-01-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Unraveling the role of post-annealing in IGZO transistor for memory applications

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-01-19 DOI: 10.1016/j.mee.2025.112322

Nayeon Kim , Jiae Jeong , Jae Woo Lee , Jiyong Woo

{"title":"Unraveling the role of post-annealing in IGZO transistor for memory applications","authors":"Nayeon Kim , Jiae Jeong , Jae Woo Lee , Jiyong Woo","doi":"10.1016/j.mee.2025.112322","DOIUrl":"10.1016/j.mee.2025.112322","url":null,"abstract":"<div><div>We demonstrate that post-annealing techniques are important for achieving the transfer characteristics of indium‑gallium‑zinc oxide (IGZO) transistors and identify that their role depends on the sputter-deposited IGZO film conditions. The as-fabricated transistor with a thin IGZO channel, HfO<sub>2</sub> gate dielectric, and Mo gate electrode exhibits a constant drain current (I<sub>DS</sub>) over gate voltage (V<sub>GS</sub>). Although the oxygen (O<sub>2</sub>) plasma gas rate is adjusted from 0.2 to 1 sccm with an argon gas rate of 30 sccm during IGZO deposition, the I<sub>DS</sub> level was reduced by a factor of 10<sup>4</sup>. Notably, V<sub>GS</sub>-controlled transfer behavior of the transistors only starts after post-annealing is performed at temperatures above 300 °C, regardless of which IGZO channel properties are used. More specifically, since oxygen vacancies (V<sub>O</sub>s) serve as carriers in the IGZO, annealing in different O<sub>2</sub> gas or air environments to generate or reduce the number of V<sub>O</sub>s is found to be optimal for the V<sub>O</sub>-rich or V<sub>O</sub>-poor channels, respectively. In this study, we reveal that oxidation annealing appears to be a more effective way for achieving improved gate controllability (e.g., subthreshold swing). Accordingly, we further analyze how the V<sub>O</sub>s in the IGZO are involved in switching by examining the effect of annealing temperature and gate dielectric materials on the transfer curve. These results indicate that V<sub>O</sub>s in the bulk need to be annihilated to lower the off-state I<sub>DS</sub>, while a sufficient number of V<sub>O</sub>s near the channel and gate dielectric interface should be ensured to responded by V<sub>GS</sub> for rapid switching.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112322"},"PeriodicalIF":2.6,"publicationDate":"2025-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low temperature solid-state diffusion bonding of fine pitch Cu/Sn micro-bumps assisted with formic acid vapor for 3D integration

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-01-17 DOI: 10.1016/j.mee.2025.112319

Hanlin Wan , Qian Wang , Jian Cai , Dejun Wang

{"title":"Low temperature solid-state diffusion bonding of fine pitch Cu/Sn micro-bumps assisted with formic acid vapor for 3D integration","authors":"Hanlin Wan , Qian Wang , Jian Cai , Dejun Wang","doi":"10.1016/j.mee.2025.112319","DOIUrl":"10.1016/j.mee.2025.112319","url":null,"abstract":"<div><div>Low-temperature solid-state diffusion (SSD) bonding of 5 μm diameter Cu/Sn micro-bumps was achieved with the assistance of formic acid vapor. Efforts were made to overcome surface oxidation of copper and uneven tin morphology, which are two major challenges in SSD bonding. Formic acid vapor was used as pre-treatment gas before bonding and protection gas during bonding. The results demonstrated that formic acid vapor is highly effective in removing surface oxidation on copper and preventing secondary oxidation, thereby facilitating a strong bond. Temperatures of 160 °C and 200 °C in 120 s were identified as ideal for pre-treatment. In SSD thermal compression bonding, 30 MPa TCB pressure was found to be necessary to overcome the uneven tin morphology. Other bonding parameters were also optimized, achieving a die shear strength of up to 59 MPa while reducing bonding temperature and time to 150 °C and 10 min. As bump scale shrinks, the interface analysis revealed a unique “teeth-like” structure in the bonding interface, contributing to improved shear strength due to intermetallic compound (IMC) growth and a favorable stress distribution. The assistance of formic acid vapor and the optimization of bonding parameters enhances the likelihood of future applications of solid-state bonding in industry, which could be an alternative choice for fine-pitch micro-bump bonding application.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112319"},"PeriodicalIF":2.6,"publicationDate":"2025-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143129836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fabrication of industrial grade GMR multilayer magnetic sensors for non-recording applications

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-01-11 DOI: 10.1016/j.mee.2024.112311

Bhagaban Behera, Umesh P. Borole, Jakeer Khan, Harish C. Barshilia, P. Chowdhury

引用次数: 0

Ultrasharp periodic AlN nanotips formed via purely subtractive nanofabrication

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2025-01-11 DOI: 10.1016/j.mee.2025.112312

Robert Fraser Armstrong , Philip Aldam Shields

引用次数: 0

Application of atomic force microscopy technology in doping characterization of semiconductor materials and devices

IF 2.6 4区工程技术

Microelectronic Engineering Pub Date : 2024-12-30 DOI: 10.1016/j.mee.2024.112310

Xiaomeng Liu, Xiangsheng Wang, Xinyou Liu, Yanpeng Song, Yiwen Zhang, Hailing Wang, Ying Zhang, Guilei Wang, Chao Zhao

{"title":"Application of atomic force microscopy technology in doping characterization of semiconductor materials and devices","authors":"Xiaomeng Liu, Xiangsheng Wang, Xinyou Liu, Yanpeng Song, Yiwen Zhang, Hailing Wang, Ying Zhang, Guilei Wang, Chao Zhao","doi":"10.1016/j.mee.2024.112310","DOIUrl":"10.1016/j.mee.2024.112310","url":null,"abstract":"<div><div>The precise characterization of the doping profile is crucial for optimizing the performance and structural integrity of semiconductor devices. As the size of semiconductor devices continues to diminish, the need of precise characterization of doping profiles has become increasingly urgent. Atomic Force Microscopy (AFM) has become a promising technique for doping profile characterization within the semiconductor field, owing to its high spatial resolution, multidimensional feature analysis, and flexibility in various working environments. Based on AFM technology, various techniques have been developed for doping characterization, such as scanning capacitance microscope (SCM), scanning spreading resistance microscope (SSRM) and scanning microwave impedance microscope (sMIM). In this work, we systematically review the application of these three techniques for doping characterization and summarize their strengths and limitations. Furthermore, we also evaluate their capability in characterizing the doping profiles of miniature devices with three-dimensional (3D) architectures. This work offers feasible approaches for advanced semiconductor device manufacturing.</div><div>© 2012 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of Global Science and Technology Forum Pte Ltd.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"297 ","pages":"Article 112310"},"PeriodicalIF":2.6,"publicationDate":"2024-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143128952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0