L.B. Avila , A. Cantudo , M.A. Villena , D. Maldonado , F. Abreu Araujo , C.K. Müller , J.B. Roldán
{"title":"Variability analysis in memristors based on electrodeposited prussian blue","authors":"L.B. Avila , A. Cantudo , M.A. Villena , D. Maldonado , F. Abreu Araujo , C.K. Müller , J.B. Roldán","doi":"10.1016/j.mee.2025.112376","DOIUrl":"10.1016/j.mee.2025.112376","url":null,"abstract":"<div><div>This work presents a comprehensive analysis of the variability and reliability of the resistive switching (RS) behavior in Prussian Blue (a mixed-valence iron(III/II) hexacyanoferrate compound) thin films, used as the active layer. These films are fabricated through a simple and scalable electrochemical process, and exhibit robust bipolar resistive switching, making them suitable both for neuromorphic computing applications and hardware cryptography. A detailed statistical evaluation was conducted over 100 consecutive switching cycles using multiple parameter extraction techniques to assess cycle-to-cycle (C2C) variability in key RS parameters, including set/reset voltages and corresponding currents. One and two-dimensional coefficients of variation (1DCV and 2DCV) were calculated to quantify variability and identify application potential. Results demonstrate moderate variability compatible with neuromorphic computing and cryptographic functionalities, including physical unclonable functions and true random number generation. These findings position Prussian Blue-based memristors as promising candidates for low-cost, stable, and multifunctional memory.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112376"},"PeriodicalIF":2.6,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144510669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Giulio Galderisi , Thomas Mikolajick , Jens Trommer
{"title":"Impact of Bias temperature instability on reconfigurable field effect transistors and circuits","authors":"Giulio Galderisi , Thomas Mikolajick , Jens Trommer","doi":"10.1016/j.mee.2025.112374","DOIUrl":"10.1016/j.mee.2025.112374","url":null,"abstract":"<div><div>Assessing the reliability of emerging device technologies is of fundamental importance to facilitate their adoption in larger scale electronic circuits and systems. This is even more true for all those devices whose unique behavior paves the way towards innovative circuit solutions, but also poses new reliability concerns that are not well known as in established technologies such as CMOS. In this paper, we thoroughly discuss the bias temperature instability (BTI) reliability features of three-independent-gate reconfigurable field effect transistors (RFETs). This multi-gate transistor technology is characterized by the unique feature of providing volatile polarity and threshold control within an individual device. While these devices are subjected to positive and negative BTI in alternating fashion during circuit operation, we identified negative BTI to be the worst-case condition with respect to performance degradation of RFETs in terms of threshold voltage shift and sub-threshold slope reduction. In addition we could reveal clear phenomenological differences in the degradation if the stress profiles are applied to the gates that turn on and off the transistors, rather than when they are applied to the ones that program their polarity. Positive BTI generally produces negligible effects on the threshold voltage shifts, while it has a certain impact on the sub-threshold slope degradation of one of the operational modes of the considered transistors.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112374"},"PeriodicalIF":2.6,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144331160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Impact of metal/semiconductor contact layout on the performance of an integrated silicon cavity-free micro thermoelectric generator","authors":"Md Mehdee Hasan Mahfuz, Shuhei Arai, Yuma Miyake, Takeo Matsuki, Takanobu Watanabe","doi":"10.1016/j.mee.2025.112365","DOIUrl":"10.1016/j.mee.2025.112365","url":null,"abstract":"<div><div>The development of nanotechnology has had a significant impact on thermoelectric generators (TEGs), which are expected to play a vital role in meeting sustainable energy requirements. In an integrated micro-thermoelectric device, any change in peripheral parts such as metal/semiconductor contacts may affect thermoelectric (TE) power generation. In this study, we evaluated the TE performance of silicon-based micro-TEGs by varying the metal/Silicon contact arrays on the hot and cold side pads to investigate the effect of the contact array in TE devices. The results show that the device's performance has been influenced by a variation of temperature gradient that happened through the silicon-nanowires due to the alternation of contact arrays.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112365"},"PeriodicalIF":2.6,"publicationDate":"2025-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144331159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S.H. Lau , W. Lo , B. Stripe , F. Su , S. Lewis , R.I. Spink , W. Yun
{"title":"A laboratory system for X-ray assisted device alteration (XADA)","authors":"S.H. Lau , W. Lo , B. Stripe , F. Su , S. Lewis , R.I. Spink , W. Yun","doi":"10.1016/j.mee.2025.112375","DOIUrl":"10.1016/j.mee.2025.112375","url":null,"abstract":"<div><div>The shift toward backside power delivery (BPD) architecture and 3D stacking of integrated circuits (ICs) introduces significant challenges for failure analysis (FA). Traditional near-infrared (NIR)-based fault isolation techniques such as Laser-Assisted Device Alteration (LADA) are rendered ineffective by NIR-blocking metallization layers. X-ray-Assisted Device Alteration (XADA) emerges as a powerful alternative, leveraging the penetrating capability of x-rays to target and alter transistor behavior. The ability of x-rays to penetrate near-infrared opaque materials is heavily exploited for non-destructive inspection of packaged parts and circuit boards. For these applications, the ability of the ionizing x-rays to alter transistor characteristics is undesirable. Recently, however, the intentional exploitation of these ionizing effects for targeted device alteration using a micro-focused, scanning x-ray beam, analogous to LADA, has been explored. This paper provides an expanded analysis of XADA, introducing advancements in x-ray source design, focusing optics, and experimental methodologies. Additionally, system-level innovations, including high-precision navigation and co-axial optical setups, position XADA as a transformative tool for FA of BPD-era ICs.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112375"},"PeriodicalIF":2.6,"publicationDate":"2025-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144322487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bernhard Pruckner , Nils Petter Jørstad , Wolfgang Goes , Siegfried Selberherr , Viktor Sverdlov
{"title":"Field-free magnetization switching in SOT-MRAM devices with noncollinear antiferromagnets","authors":"Bernhard Pruckner , Nils Petter Jørstad , Wolfgang Goes , Siegfried Selberherr , Viktor Sverdlov","doi":"10.1016/j.mee.2025.112372","DOIUrl":"10.1016/j.mee.2025.112372","url":null,"abstract":"<div><div>Spin-orbit torque magnetoresistive random access memory (SOT-MRAM) is a promising nonvolatile memory technology that offers fast writing speed, low power, and long endurance. However, achieving deterministic perpendicular magnetization switching typically requires an external field, limiting scalability. This work explores the incorporation of noncollinear antiferromagnetic (nc-AFMs), exhibiting the magnetic spin Hall effect (MSHE), and exchange bias to enable field-free deterministic switching. MSHE has been observed in Mn<span><math><msub><mrow></mrow><mn>3</mn></msub></math></span>Sn, MnPd<span><math><msub><mrow></mrow><mn>3</mn></msub></math></span>. The ratio of out-of-plane to in-plane polarized spin-currents is crucial for field-free MSHE-driven magnetization switching. It was found that a minimum ratio is needed to drive field-free perpendicular switching. Exchange bias acting at the interface between in-plane AFM and out-of-plane ferromagnet (FM) has been demonstrated to enable field-free SOT-driven magnetization switching. We show, that exchange bias can facilitate field-free perpendicular switching in cases of a missing or too small out-of-plane polarized spin current component. We present a fully three-dimensional finite element model that couples spin currents and magnetization dynamics to simulate SOT-MRAM devices utilizing the MSHE. We show that the use of nc-AFMs eliminates the need for external fields without compromising performance, simplifying design, and boosting scalability.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112372"},"PeriodicalIF":2.6,"publicationDate":"2025-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144263517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Boshang Lu , Hu Zhao , Jiayu Ma , Jian Wang , Qian Li , Wei Xun , Daixuan Wu
{"title":"Electrothermal-coupled flexible microwave resonant icing sensor Array","authors":"Boshang Lu , Hu Zhao , Jiayu Ma , Jian Wang , Qian Li , Wei Xun , Daixuan Wu","doi":"10.1016/j.mee.2025.112360","DOIUrl":"10.1016/j.mee.2025.112360","url":null,"abstract":"<div><div>This paper proposes an ice prevention and de-icing flexible microwave sensor array based on electrothermal coupling. The flexible sensor array uses the principle of microwave resonance to detect ice thickness and shape, integrating an electric heating moduleto achieve integrated ice prevention and de-icing functions. Ice detection employs a complementary coupled crack ring resonator (CCSRR) structure sensitive to ice layer thickness, while electric heating de-icing is achieved through a flexible structure of PI(Polyimide) substrate heating wires, combined with NTC(Negative Temperature Coefficient Thermistor) for real-time temperature feedback. Low-power operation mode of electric heating film module endowing the system with certain anti-icing capabilities. Additionally, the sensor array is fully flexible, making it easy to install on areas prone to icing on drones, thus preventing icing from affecting flight safety. The array sensor can perform multi-point measurements to obtain ice shape information. First, a single electrothermal coupling ice prevention and de-icing integrated sensor element was fabricated, and a S21 parameter testing platform was established to verify the ice detection and de-icing capabilities of the sensor array system. The results show that the designed sensor array can distinguish 0.1 mm ice layers. In a-10 °C environment, electrothermal de-icing experiments demonstrated that 4 mm ice layers could be completely melted within 20 s. The heating effect of the sensor array is ideal; preheating can effectively prevent icing, and the degree of de-icing can be simultaneously determined during the de-icing process. The Low-power operation mode of electric heating film module ensures that when icing occurs on the system surfaceThe delay is doubled, and the energy consumption of single electric heating anti-icing is reduced by half. It proves that the ice sensor array has good ice detection and anti-icing ability.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112360"},"PeriodicalIF":2.6,"publicationDate":"2025-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144366962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Unsupervised domain adaptation for IC image segmentation with structural constraint and pseudo supervision","authors":"Deruo Cheng, Yee-Yang Tee, Xuenong Hong, Tong Lin, Yiqiong Shi, Bah-Hwee Gwee","doi":"10.1016/j.mee.2025.112373","DOIUrl":"10.1016/j.mee.2025.112373","url":null,"abstract":"<div><div>Integrated circuit (IC) image segmentation is crucial for functional verification and trustworthiness evaluation of ICs manufactured in the globalized supply chain. Conventional supervised deep learning models for IC image segmentation face significant challenges of domain shift when applied across IC layers. To address this, we propose a domain adaptation framework with Structural Constraint and Pseudo Supervision (SCPS) for improving segmentation performance on target datasets collected from different IC layers. Our proposed SCPS first leverages CycleGAN to synthesize target dataset with input masks from source dataset, where a constraint is imposed onto the structural patterns of circuit elements in synthetic target images and source masks to improve their structural consistency. It further utilizes unlabeled real target images through domain mixing and image−/feature-level augmentation with pseudo supervision during training. With experiments on target datasets collected from two different IC chip layers, our proposed SCPS outperforms existing methods in the accuracy of circuit connections retrieved from IC image segmentation, while maintaining comparable performance in terms of commonly used segmentation metrics.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112373"},"PeriodicalIF":2.6,"publicationDate":"2025-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144263516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Daixuan Wu , Boshang Lu , Zhiyuan Xu , Qian Li , Jian Wang , Wei Xun , Hu Zhao
{"title":"Research on stress mutation of fiber optic gyroscope","authors":"Daixuan Wu , Boshang Lu , Zhiyuan Xu , Qian Li , Jian Wang , Wei Xun , Hu Zhao","doi":"10.1016/j.mee.2025.112362","DOIUrl":"10.1016/j.mee.2025.112362","url":null,"abstract":"<div><div>Temperature-variation sensitivity of fiber-optic rings is a bottleneck problem that restricts the engineering application of fiber optic gyroscopes in high-precision fields. At present, techniques such as quadrupole-symmetry and octupole-symmetry schemes are commonly used to enhance the length and position symmetry of fiber optic rings, achieving mutual cancellation of external temperature changes. This article is based on engineering applications, focusing on the conventional symmetry of fiber optic rings, and focusing on the process factors that affect the stress symmetry of fiber optic rings. It is found that there is a significant stress mutation in the bottom layer of the fiber optic ring using the conventional four pole and eight pole symmetric winding schemes. By analyzing the curing mechanism and the stress curve before and after curing, it is found that the tension of the fiber optic ring is affected. The difference in modulus between the fiber optic and the skeleton jointly causes a sudden change in the underlying stress curve. This paper proposes a buffer layer design method with batch-producible process, which can effectively suppress stress mutations in the central area of the fiber optic ring. The gyroscope products equipped with this process fiber optic ring can improve the temperature and bias instability index by 29 % while ensuring vibration performance. It has successfully achieved batch production of 0.01°/h fiber-optic gyroscopes, completed the production and development of over 3000 axes, and demonstrated significant engineering application value</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112362"},"PeriodicalIF":2.6,"publicationDate":"2025-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144290509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Kaltzoglou , E. Christopoulos , D.N. Kossyvakis , N.S. Tagiara , P. Falaras , N.K. Nasikas , E.V. Hristoforou , M.M. Elsenety
{"title":"Assessing the performance of perovskite solar cells under Peltier cooling","authors":"A. Kaltzoglou , E. Christopoulos , D.N. Kossyvakis , N.S. Tagiara , P. Falaras , N.K. Nasikas , E.V. Hristoforou , M.M. Elsenety","doi":"10.1016/j.mee.2025.112364","DOIUrl":"10.1016/j.mee.2025.112364","url":null,"abstract":"<div><div>The commercialization of perovskite solar cells (PSCs) has been restricted so far due to their short life time, which is partly attributed to their instability at high operating temperatures. The current paper studies the performance of the cells under Peltier cooling. The experimental setup includes a perovskite solar cell and a Peltier cooler beneath, where the latter is connected to an external power supply. The temperature on the surface of the solar cell spans over the range ca. 5 °C to 50 °C under 1 sun illumination, depending on the power input of the Peltier cooler. The <em>J</em>-<em>V</em> measurements indicate a non-linear temperature dependence of the power conversion efficiency (PCE), which reaches a maximum of 18.1 % at 27 °C, whereas at temperatures close to 50 °C the PCE drops significantly. The experimental results are combined with more generic theoretical simulations for scaling up the PSC unit, which provides electrical power to the Peltier unit. The simulations examine the ability of different system configurations to maintain the solar cell temperature below 50 °C without significant deterioration of the electrical performance of the hybrid PSC – Peltier device. Overall, the results show that a large-scale PSC – Peltier device is feasible for both roof-integrated and rooftop installation types, in order to protect the solar cell from overheating and degradation.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"299 ","pages":"Article 112364"},"PeriodicalIF":2.6,"publicationDate":"2025-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144166750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Vidar Flodgren , Abhijit Das , Joachim E. Sestoft , Nathanael Löfström , David Alcer , Hossein Jeddi , Magnus T. Borgström , Håkan Pettersson , Jesper Nygård , Anders Mikkelsen
{"title":"Flexible fabrication of aligned multi-nanowire circuits for on-chip prototyping","authors":"Vidar Flodgren , Abhijit Das , Joachim E. Sestoft , Nathanael Löfström , David Alcer , Hossein Jeddi , Magnus T. Borgström , Håkan Pettersson , Jesper Nygård , Anders Mikkelsen","doi":"10.1016/j.mee.2025.112363","DOIUrl":"10.1016/j.mee.2025.112363","url":null,"abstract":"<div><div>Circuits of multiple deterministically positioned semiconductor nanowires (NWs) is the basis of many devices for photonic, quantum, or conventional transistor applications. To explore and iterate on the design of larger circuits, the means to quickly place and electrically evaluate NWs at target locations must be developed. We propose and demonstrate a multi-NW circuit building concept on SiO<sub>2</sub>/Si substrates, which enables us to quickly position and orient NW components into pre-designed configurations. Micro-manipulator probes are used to guide the NWs into reactive ion etched trenches, with desired designs, before contact metallization. The positioning works over a wide combination of trench widths and depths. Positioning accuracies are contingent on EBL patterning, precise up to ±10 nm. To demonstrate the concept, we create circuits of InP and InAs NWs with a wide variety of specific orientations. The concept was used to iterate a procedure for creating optimal contacts for InP NW photodiodes. Subsequently, we could fabricate and electrically probe 54 fully operational nano-photodiodes placed on three different samples, from which considerable statistics of diode performance could be obtained. Fabrication steps are directly compatible with conventional Si CMOS architecture and should function for a wide range of NW types. The accuracy and rate of placement combined with high fabrication yields enables proof-of-concept prototyping of complex circuits.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"300 ","pages":"Article 112363"},"PeriodicalIF":2.6,"publicationDate":"2025-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144205248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}