Improving electrical performance and reliability of stacked SiGe/Si FinFETs using O3 passivation for I/O devices

Abstract

In this work, O₃ passivation technology for the novel stacked SiGe/Si FinFET input-output (I/O) devices was investigated. First, the O₃ passivation technology was validated based on SiGe MOS capacitance (CAP) structure., with results indicating that interface state density (D_it) can be reduced to 5.12 × 10¹² eV⁻¹ cm⁻². Then, to improve the electrical performance of the stacked SiGe/Si FinFET I/O device, the O₃ passivation technology was introduced between the SiGe/Si fin and gate oxide. As a result, the electrical performance for the stacked SiGe/Si FinFET I/O device was significantly improved. For example, SS could be reduced from the 168 mV/dec to 113 mV/dec, and g_m could be improved from the 62 μS to 94 μS, which was mainly attributed to the O₃ passivation resulting in the reduction of D_it. Furthermore, its reliability assessment was also performed. The result confirmed that threshold voltage (V_TH) drift under negative bias temperature instability (NBTI) and hot carrier injection (HCI) stress were improved by 52.1 % and 60.3 %, respectively. Meanwhile, its maximum operating voltage (V_max) for a 10 years lifetime at a failure rate of 0.01 % could reach to 2.65 V. Therefore, the O₃ passivation process is practical for the stacked SiGe/Si I/O FinFET device in advanced GAA platforms.