A novel cu filling method for high-aspect-ratio (AR) nano-scale TSVs

Abstract

Nano-scale through‑silicon vias (n-TSVs) plays the key role in connecting the active front-side of devices and the backside power delivery network (BS-PDN) in the three-dimensional integrated circuit (3D IC). High-quality Cu filling is the most important in the n-TSVs fabrication. As the diameter decreases and the aspect ratio (AR) increases, the challenges associated with seed layer deposition, surface pre-wetting, and electrochemical deposition (ECD) will intensify. In this study, the electron beam induced deposition (EBID) method has been first proposed to deposit the seed layer for high-AR n-TSVs. Additionally, isopropanol pre-wetting is proposed to enhance surface wettability, thereby eliminating air bubbles within the via and ensuring complete filling of the electrolyte. Finally, the effect of electrolyte additives and current density on the ECD process have also been extensively investigated. The thickness of seed layer deposited by EBID exhibits high step coverage, uniformity and continuity at the top and the bottom of via. Meanwhile, the wettability of seed layer surface treated by isopropanol has been greatly increased. During the ECD process, the deposition rate of Cu is main affected by the suppressor. Besides, the current density should be chosen within a moderate value (≥ 0.03 A/dm² and ≤ 0.3 A/dm²), which can increase the deposition rate and avoid the premature closing of the via opening. With the optimized processes above, the n-TSVs of Type-I (440-nm-diameter and 4.81:1-AR) and Type-II (150-nm-diameter and 9.25:1-AR) have been conformally filled without voids and breaks.