揭示后退火在IGZO晶体管存储应用中的作用

IF 2.6 4区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Nayeon Kim , Jiae Jeong , Jae Woo Lee , Jiyong Woo
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引用次数: 0

摘要

我们证明了后退火技术对于实现铟镓锌氧化物(IGZO)晶体管的转移特性是重要的,并确定了它们的作用取决于溅射沉积的IGZO薄膜条件。采用薄IGZO沟道、HfO2栅极电介质和Mo栅极电极制备的晶体管具有恒定漏极电流(IDS)过栅电压(VGS)。虽然在IGZO沉积过程中,氧气(O2)等离子体气体速率从0.2 sccm调整到1 sccm,氩气速率为30 sccm,但IDS水平降低了104倍。值得注意的是,无论使用哪种IGZO通道特性,晶体管的vgs控制转移行为仅在300°C以上的温度下进行后退火后才开始。更具体地说,由于氧空位(VOs)在IGZO中充当载流子,因此在不同的O2气体或空气环境中退火以产生或减少VOs的数量分别是富VOs通道或贫VOs通道的最佳选择。在这项研究中,我们发现氧化退火似乎是实现改进栅极可控性(例如,亚阈值摆动)的更有效方法。因此,我们通过考察退火温度和栅极介电材料对转移曲线的影响,进一步分析了IGZO中VOs是如何参与开关的。这些结果表明,为了降低失态IDS,需要湮灭本体中的VOs,同时要保证在通道和栅极介电界面附近有足够数量的VOs来响应VGS以实现快速切换。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Unraveling the role of post-annealing in IGZO transistor for memory applications
We demonstrate that post-annealing techniques are important for achieving the transfer characteristics of indium‑gallium‑zinc oxide (IGZO) transistors and identify that their role depends on the sputter-deposited IGZO film conditions. The as-fabricated transistor with a thin IGZO channel, HfO2 gate dielectric, and Mo gate electrode exhibits a constant drain current (IDS) over gate voltage (VGS). Although the oxygen (O2) plasma gas rate is adjusted from 0.2 to 1 sccm with an argon gas rate of 30 sccm during IGZO deposition, the IDS level was reduced by a factor of 104. Notably, VGS-controlled transfer behavior of the transistors only starts after post-annealing is performed at temperatures above 300 °C, regardless of which IGZO channel properties are used. More specifically, since oxygen vacancies (VOs) serve as carriers in the IGZO, annealing in different O2 gas or air environments to generate or reduce the number of VOs is found to be optimal for the VO-rich or VO-poor channels, respectively. In this study, we reveal that oxidation annealing appears to be a more effective way for achieving improved gate controllability (e.g., subthreshold swing). Accordingly, we further analyze how the VOs in the IGZO are involved in switching by examining the effect of annealing temperature and gate dielectric materials on the transfer curve. These results indicate that VOs in the bulk need to be annihilated to lower the off-state IDS, while a sufficient number of VOs near the channel and gate dielectric interface should be ensured to responded by VGS for rapid switching.
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来源期刊
Microelectronic Engineering
Microelectronic Engineering 工程技术-工程:电子与电气
CiteScore
5.30
自引率
4.30%
发文量
131
审稿时长
29 days
期刊介绍: Microelectronic Engineering is the premier nanoprocessing, and nanotechnology journal focusing on fabrication of electronic, photonic, bioelectronic, electromechanic and fluidic devices and systems, and their applications in the broad areas of electronics, photonics, energy, life sciences, and environment. It covers also the expanding interdisciplinary field of "more than Moore" and "beyond Moore" integrated nanoelectronics / photonics and micro-/nano-/bio-systems. Through its unique mixture of peer-reviewed articles, reviews, accelerated publications, short and Technical notes, and the latest research news on key developments, Microelectronic Engineering provides comprehensive coverage of this exciting, interdisciplinary and dynamic new field for researchers in academia and professionals in industry.
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