Farid Sebaai , Roger Loo , Anne Jourdain , Eric Beyne , Hikaru Kawarazaki , Teppei Nakano , Efrain Altamirano Sanchez
{"title":"用于背面输电网络的极端硅减薄:在按比例硅锗蚀刻停止层上停止硅减薄","authors":"Farid Sebaai , Roger Loo , Anne Jourdain , Eric Beyne , Hikaru Kawarazaki , Teppei Nakano , Efrain Altamirano Sanchez","doi":"10.1016/j.mee.2024.112246","DOIUrl":null,"url":null,"abstract":"<div><p>This paper discusses the challenges relative to the silicon thinning which allows the back side power delivery integration (BSPDN). The back side silicon thinning stopping on a thin Si<sub>0.75</sub>Ge<sub>0.25</sub> etch stop layer (ESL) has been investigated as it represents an alternative to the use of SOI wafers. Etch stop layers using 10 nm Si<sub>0.75</sub>Ge<sub>0.25</sub> or 10 nm Si<sub>0.75</sub>Ge<sub>0.25</sub> boron doped (Si<sub>0.75</sub>Ge<sub>0.25</sub>:B) have been studied for which different thinning process sequences were considered. All the considered thinning sequences are terminated with a diluted ammonia (NH<sub>4</sub>OH) process which provides the selectivity towards the ESL. Considering a 10 nm Si<sub>0.75</sub>Ge<sub>0.25</sub>:B as an ESL considerably increases the selectivity of the last diluted NH<sub>4</sub>OH silicon etching step. It nevertheless induces a risk of device poisoning caused by the diffusion of boron. Considering a 10 nm Si<sub>0.75</sub>Ge<sub>0.25</sub> as an ESL has been then demonstrated using different thinning process sequences. Those alternative thinning sequences were optimized with respect to the silicon removal within wafer uniformity.</p></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":null,"pages":null},"PeriodicalIF":2.6000,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Extreme silicon thinning for back side power delivery network: Si thinning stopping on scaled SiGe etch stop layer\",\"authors\":\"Farid Sebaai , Roger Loo , Anne Jourdain , Eric Beyne , Hikaru Kawarazaki , Teppei Nakano , Efrain Altamirano Sanchez\",\"doi\":\"10.1016/j.mee.2024.112246\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>This paper discusses the challenges relative to the silicon thinning which allows the back side power delivery integration (BSPDN). The back side silicon thinning stopping on a thin Si<sub>0.75</sub>Ge<sub>0.25</sub> etch stop layer (ESL) has been investigated as it represents an alternative to the use of SOI wafers. Etch stop layers using 10 nm Si<sub>0.75</sub>Ge<sub>0.25</sub> or 10 nm Si<sub>0.75</sub>Ge<sub>0.25</sub> boron doped (Si<sub>0.75</sub>Ge<sub>0.25</sub>:B) have been studied for which different thinning process sequences were considered. All the considered thinning sequences are terminated with a diluted ammonia (NH<sub>4</sub>OH) process which provides the selectivity towards the ESL. Considering a 10 nm Si<sub>0.75</sub>Ge<sub>0.25</sub>:B as an ESL considerably increases the selectivity of the last diluted NH<sub>4</sub>OH silicon etching step. It nevertheless induces a risk of device poisoning caused by the diffusion of boron. Considering a 10 nm Si<sub>0.75</sub>Ge<sub>0.25</sub> as an ESL has been then demonstrated using different thinning process sequences. Those alternative thinning sequences were optimized with respect to the silicon removal within wafer uniformity.</p></div>\",\"PeriodicalId\":18557,\"journal\":{\"name\":\"Microelectronic Engineering\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.6000,\"publicationDate\":\"2024-07-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronic Engineering\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0167931724001151\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronic Engineering","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167931724001151","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Extreme silicon thinning for back side power delivery network: Si thinning stopping on scaled SiGe etch stop layer
This paper discusses the challenges relative to the silicon thinning which allows the back side power delivery integration (BSPDN). The back side silicon thinning stopping on a thin Si0.75Ge0.25 etch stop layer (ESL) has been investigated as it represents an alternative to the use of SOI wafers. Etch stop layers using 10 nm Si0.75Ge0.25 or 10 nm Si0.75Ge0.25 boron doped (Si0.75Ge0.25:B) have been studied for which different thinning process sequences were considered. All the considered thinning sequences are terminated with a diluted ammonia (NH4OH) process which provides the selectivity towards the ESL. Considering a 10 nm Si0.75Ge0.25:B as an ESL considerably increases the selectivity of the last diluted NH4OH silicon etching step. It nevertheless induces a risk of device poisoning caused by the diffusion of boron. Considering a 10 nm Si0.75Ge0.25 as an ESL has been then demonstrated using different thinning process sequences. Those alternative thinning sequences were optimized with respect to the silicon removal within wafer uniformity.
期刊介绍:
Microelectronic Engineering is the premier nanoprocessing, and nanotechnology journal focusing on fabrication of electronic, photonic, bioelectronic, electromechanic and fluidic devices and systems, and their applications in the broad areas of electronics, photonics, energy, life sciences, and environment. It covers also the expanding interdisciplinary field of "more than Moore" and "beyond Moore" integrated nanoelectronics / photonics and micro-/nano-/bio-systems. Through its unique mixture of peer-reviewed articles, reviews, accelerated publications, short and Technical notes, and the latest research news on key developments, Microelectronic Engineering provides comprehensive coverage of this exciting, interdisciplinary and dynamic new field for researchers in academia and professionals in industry.